Bit rate control over groups of frames

1. A method for processing data from a sequential series of groups of frames to achieve a target average processing bit rate for a particular group of frames in the series, the series including a first group of frames F 1 through a last group of frames Fj, wherein each group of frames comprises Dj frames, the method comprising:

receiving B 1 frames of the first group of frames F 1 in a look-ahead processing buffer, the received frames including a first buffered frame F 1 0 through frame F 1 B1−1 , wherein B 1 is greater than 1 and B 1 is less than D 1 ;

determining, using a processor circuit, a first bit allocation for the first buffered frame F 1 0 based on one or more bit allocation requests corresponding to the received B 1 frames in the look-ahead processing buffer;

receiving, in the look-ahead processing buffer, a last frame F 1 D1−1 of the first group of frames F 1 to be encoded; and

determining, using the processor circuit, a subsequent bit allocation for the last frame F 1 D1−1 based on fewer than B 1 bit allocation requests.

2. The method of claim 1 , further comprising:

determining bit allocations for one or more other frames in the first group of frames F 1 preceding the last frame F 1 D1−1 ; and

expunging frames other than the last frame F 1 D1−1 from the look-ahead processing buffer;

wherein the determining the subsequent bit allocation for the last frame F 1 D1−1 of the first group of frames F 1 includes using a bit allocation request corresponding to only the last frame F 1 D1−1 .

3. The method of claim 1 , wherein the receiving the B 1 frames of the first group of frames F 1 in the look-ahead processing buffer includes receiving B 1 respective bit allocation requests for the B 1 received frames; and

wherein the determining the first bit allocation for the first buffered frame F 1 0 includes using information about each of the B 1 bit allocation requests corresponding to the received B 1 frames in the look-ahead processing buffer.

4. The method of claim 1 , further comprising encoding, using the same or other processor circuit, the first buffered frame F 1 0 using the first bit allocation.

5. The method of claim 1 , further comprising:

updating frame contents of the look-ahead processing buffer including removing the first buffered frame F 1 0 and receiving a later frame F 1 B1 such that the look-ahead processing buffer includes a second buffered frame F 1 1 through frame F 1 B1 ; and

determining, using the processor circuit, a bit allocation for the second buffered frame F 1 1 based on B 1 bit allocation requests corresponding to the updated frame contents of the look-ahead processing buffer.

6. The method of claim 1 , further comprising:

before encoding the last frame F 1 D1−1 from the first group of frames F 1 , buffering bit allocation requests for one or more frames of a subsequent second group of frames F 2 .

7. The method of claim 1 , further comprising:

before encoding the last frame F 1 D1−1 from the first group of frames F 1 :

populating a portion of a second look-ahead processing buffer with frames from a second group of frames F 2 , including receiving at least frame F 2 0 ;

following determining the subsequent bit allocation for the last frame F 1 D1−1 from the first group of frames F 1 :

filling the second look-ahead processing buffer with at least one additional frame of the second group of frames F 2 , the received frames including B 2 frames F 2 0 through F 2 B2−1 , wherein B 2 is greater than 1; and

determining, using the processor circuit, a bit allocation for the frame F 2 0 based on one or more bit allocation requests corresponding to the received B 2 frames in the second look-ahead processing buffer;

receiving, in the second look-ahead processing buffer, a last frame F 2 D2−1 of the second group of frames F 2 to be encoded, and expunging frames other than the last frame F 2 D2−1 from the second look-ahead processing buffer; and

determining, using the processor circuit, a bit allocation for the last frame F 2 D2−1 based on fewer than B 2 bit allocation requests.

8. The method of claim 1 , further comprising determining one or more constraints associated with the frames in the first group of frames F 1 , wherein the determining the one or more constraints includes one or more of:

determining a maximum bit rate or a minimum bit rate for a particular frame or group of frames;

determining a constraint that applies to multiple ones of the frames in the first group of frames F 1 ; and

determining respective constraints for each of the frames in the first group of frames F 1 .

9. The method of claim 1 , further comprising:

identifying a relative or absolute perceptual importance of the information in the frames of the first group of frames F 1 ; and

allocating a greater number of bits to the first frame F 1 0 than to a subsequent second frame F 1 1 when a perceptual importance of information in the first frame F 1 0 exceeds a perceptual importance of information in the second frame F 1 1 .

10. A method for processing data from a sequential series of groups of frames, including a first group of frames F 1 through a last group of frames Fj, wherein each group of frames comprises Dj frames, including a first frame Fn 0 through a last frame Fn Dj−1 , the method comprising:

receiving a first series of frames in a first buffer of size B frames, the first series of frames including frames F 1 0 through F 1 B−1 from the first group of frames F 1 , wherein B is less than a total number of frames D 1 in the first group of frames F 1 ;

encoding a first frame F 1 0 of the first group of frames F 1 , including:

receiving, at a first processor circuit, respective bit allocation requests for the first series of frames in the first buffer, the bit allocation requests based on constraints associated with the first series of frames in the first buffer;

determining, using the first processor circuit, a first bit allocation for the first frame F 1 0 based on at least one of the constraints associated with the first series of frames in the first buffer; and

encoding the first frame F 1 0 using the determined first bit allocation for the first frame F 1 0 ;

updating the first buffer to include a second series of frames, the second series of frames including frames F 1 1 through F 1 B from the first group of frames F 1 ;

encoding a second frame F 1 1 of the first group of frames F 1 , including:

receiving, at the first processor circuit, respective bit allocation requests for the second series of frames in the updated first buffer, the bit allocation requests based on constraints associated with the second series of frames in the updated first buffer;

determining, using the first processor circuit, a second bit allocation for the second frame F 1 1 based on at least one of the constraints associated with the second series of frames in the updated first buffer; and

encoding the second frame F 1 1 using the determined second bit allocation for the second frame F 1 1 .

11. The method of claim 10 , wherein the determining the first bit allocation for the first frame F 1 0 includes determining the first bit allocation using information about the bit allocation requests for all of the frames in the first series of frames in the first buffer.

12. The method of claim 10 , wherein the determining the first and second bit allocations for the first frame F 1 0 and the second frame F 1 1 , respectively, includes satisfying a first target average bit rate for the first group of frames F 1 .

13. The method of claim 10 , wherein the receiving the respective bit allocation requests for the first series of frames in the first buffer includes receiving requests that are based on constraints that include one or more of a minimum bit rate and a maximum bit rate.

14. The method of claim 10 , wherein the determining the first and second bit allocations for the first frame F 1 0 and the second frame F 1 1 , respectively, includes allocating the bits based on a relative perceptual importance of information in the first frame F 1 0 and the second frame F 1 1 .

15. A system for processing data from a sequential series of groups of frames to achieve a target average processing bit rate for a particular group of frames in the series, the series including a first group of frames F 1 through a last group of frames Fj, wherein each group of frames comprises Dj frames, the system comprising:

a look-ahead buffer circuit configured to receive B 1 frames of the first group of frames F 1 , the received frames including a first buffered frame F 1 0 through frame F 1 B1−1 , wherein B 1 is greater than 1 and B 1 is less than D 1 ;

a bit allocation processor circuit, coupled to the look-ahead buffer circuit, the bit allocation processor circuit configured to determine a first bit allocation for the first buffered frame F 1 0 based on the bit allocation requests corresponding to the received B 1 frames in the look-ahead processing buffer wherein the received B 1 frames include fewer than all of the frames from the first group of frames F 1 ; and

an encoder circuit configured to encode the first buffered frame F 1 0 using the determined first bit allocation.

16. The system of claim 15 , wherein the look-ahead buffer circuit is configured to receive new frames from the first group of frames F 1 and expunge old frames from the first group of frames F 1 in a first-in-first-out manner.

17. The system of claim 15 , wherein the bit allocation processor circuit is configured to determine a bit allocation for a second buffered frame F 1 1 based on bit allocation requests corresponding to B 1 frames, F 1 1 through F 1 B1 , in the look-ahead processing buffer.

18. The system of claim 15 , wherein the bit allocation processor circuit is configured to determine the first bit allocation based on constraints associated with one or more frames in the first group of frames F 1 or in another group of frames.

19. The system of claim 15 , wherein the bit allocation processor circuit is configured to determine the first bit allocation based on a relative perceptual importance characteristic of the first buffered frame F 1 0 with respect to other frames in the first group of frames F 1 .

20. The system of claim 15 , wherein the look-ahead buffer circuit is configured to receive the frames as a continuous data stream arriving from a network.