METHODS OF FORMING SEGMENTED VIAS FOR PRINTED CIRCUIT BOARDS
Novel methods for forming a printed circuit board (PCB) having one or more segmented vias are provided, including improved methods of removing the catalyst after the plating process when forming a segmented via in the PCB. After the electroless plating, excess catalyst on the surface of the plating resist is removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating is then applied to the through holes and the outer layer circuit or signal traces are formed. That is, the etching of paths on the conductive foils/layers of the core structure.
1 . A method for making a printed circuit board having a segmented plated through hole, comprising:
forming a core or sub-composite structure;
selectively depositing at least one plating resist on a dielectric layer within the core or sub-composite structure or external to the core or sub-composite structure;
forming one or more through holes through the core or sub-composite structure and the plating resist; and
applying a catalyzing material to an interior surface of the one or more through holes, the interior surface having a laminate portion and a plating resist portion where only the laminate portion is coated with a conductive material;
applying electroless plating to the one or more through holes;
removing the catalyzing material from the plating resist portion using a catalyst remover;
applying electrolytic plating to the one or more through holes; and
forming an outer layer circuit on the external conductive layers.
2 . The method of claim 1 , wherein the catalyzing material is palladium or a palladium derivative.
3 . The method of claim 1 , wherein the catalyst remover is an acidic solution and wherein the acidic solution includes at least nitrite or nitrite ion and halogen ion.
4 . The method of claim 1 , wherein the catalyst remover is an etchant for plating resist.
5 . The method of claim 4 , wherein the etchant is an alkaline permanganate compound solution.
6 . The method of claim 5 , wherein the etchant is plasma gas.
7 . The method of claim 6 , wherein the plasma gas includes at least one of oxygen, nitrogen, argon and tetrafluoromethane.
8 . A method for making a printed circuit board having a segmented plated through hole, comprising:
forming a core or sub-composite structure;
selectively depositing at least one plating resist on a dielectric layer within the core or sub-composite structure or external to the core or sub-composite structure;
forming a through hole through the core or sub-composite structure and the plating resist;
applying a catalyzing material to an interior surface of the one or more through holes, the interior surface having a laminate portion and a plating resist portion where only the laminate surface is to be coated with a conductive material
applying metal plating to the one or more through holes;
removing the catalyzing material from the plating resist portion using a catalyst remover; and
forming an outer layer circuit on the conductive layers of the first core.
9 . The method of claim 8 , wherein the catalyzing material is palladium or a palladium derivate.
10 . The method of claim 9 , wherein the catalyst remover is an acidic solution and wherein the acidic solution includes at least nitrite or nitrite ion and halogen ion.
11 . The method of claim 8 , wherein the catalyst remover is an etchant for plating resist.
12 . The method of claim 11 , wherein the etchant is an alkaline permanganate compound solution.
13 . The method of claim 11 , wherein the etchant is plasma gas and wherein the plasma gas includes at least one of oxygen, nitrogen, argon and tetrafluoromethane.
14 . A method for making a printed circuit board having a segmented plated through hole, comprising:
forming a core or sub-composite structure;
selectively depositing at least one plating resist on a dielectric layer within the core or sub-composite structure or external to the core or sub-composite structure;
forming a through hole through the core or sub-composite structure and the plating resist; and
applying a catalyzing material to an interior surface of the one or more through holes, the interior surface having a laminate portion and a plating resist portion where the laminate surface is to be coated with a conductive material and the plating resist portion is not to be plated with a conductive material;
applying metal plating to the one or more through holes;
forming an outer layer circuit on the conductive layers of the first core; and
removing the catalyzing material from the plating resist portion and dielectric material surface using a catalyst remover.
15 . The method of claim 14 , wherein the catalyzing material is palladium or a palladium derivate.
16 . The method of claim 14 , wherein the catalyst remover is an acidic solution.
17 . The method of claim 16 , wherein the acidic solution includes at least nitrite or nitrite ion and halogen ion.
18 . The method of claim 14 , wherein the catalyst remover is an etchant for plating resist.
19 . The method of claim 18 , wherein the etchant is an alkaline permanganate compound solution.
20 . The method of claim 19 , wherein the etchant is plasma gas and wherein the plasma gas includes at least one of oxygen, nitrogen, argon and tetrafluoromethane.