IP Library Granted Patent US 10,579,529
Granted Patent B2
US 10,579,529 · App. 15/964,315 · Granted Mar 3, 2020

Reducing overhead of managing cache areas

Inventors: Venkata Khambam (Cork, IE); Jeffrey R. Nelson (Dunstable, MA); Brian Asselin (Upton, MA); Rong Yu (West Roxbury, MA)
Assignee: EMC IP Holding Company LLC
G06F12/084G06F12/0815G06F12/0842G06F2212/621
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Quick Facts
Patent No.
US 10,579,529
App. No.
15/964,315
Granted
Mar 3, 2020
Kind
B2
Abstract

Maintaining multiple cache areas in a storage device having multiple processors includes loading data from a specific portion of non-volatile storage into a local cache slot in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the local cache slot is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and includes converting the local cache slot into a global cache slot in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache area is accessible to the first subset of the processors and to the second subset of the processors. Different ones of the processors may be placed on different directors.

Claims (24)

1. A method of maintaining multiple cache areas in a storage device having multiple processors, comprising:

loading data from a specific portion of non-volatile storage into a local cache slot in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, wherein the local cache slot is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors; and

converting the local cache slot into a global cache slot in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache slot is accessible to the first subset of the processors and to the second subset of the processors.

2. A method, according to claim 1 , wherein different ones of the processors are placed on different directors.

3. A method, according to claim 2 , wherein the global cache slot and the local cache slot are provided by memory on the directors.

4. A method, according to claim 3 , wherein a portion of the memory corresponding to the global cache slot is accessible to all of the directors.

5. A method, according to claim 3 , wherein a portion of the memory corresponding to the local cache slot is only accessible by processors on a same one of the directors as the portion of the memory.

6. A method, according to claim 1 , wherein following loading the data into the local cache slot, storage of the data in the global cache slot is cancelled.

7. A method, according to claim 1 , wherein the data from the local cache slot is provided to the specific processor independent of completing modifying system metadata indicating that the data has been loaded into the local cache slot.

8. A method, according to claim 1 , wherein prior to loading the data in to the local cache slot, prior data is removed from the local cache slot.

9. A method, according to claim 8 , wherein removing the prior data includes initiating a metadata modification corresponding thereto, wherein the prior data is removed independent of completion of modification of the metadata.

10. A method, according to claim 1 , wherein prior to converting the local cache slot into a global cache slot, the local cache slot is chosen from a plurality of local cache slots that contain the data.

11. A non-transitory computer readable medium containing software that maintains multiple cache areas in a storage device having multiple processors, the software comprising:

executable code that loads data from a specific portion of non-volatile storage into a local cache slot in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, wherein the local cache slot is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors; and

executable code that converts the local cache slot into a global cache slot in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache slot is accessible to the first subset of the processors and to the second subset of the processors.

12. A non-transitory computer readable medium, according to claim 11 , wherein different ones of the processors are placed on different directors.

13. A non-transitory computer readable medium, according to claim 12 , wherein the global cache slot and the local cache slot are provided by memory on the directors.

14. A non-transitory computer readable medium, according to claim 13 , wherein a portion of the memory corresponding to the global cache slot is accessible to all of the directors.

15. A non-transitory computer readable medium, according to claim 13 , wherein a portion of the memory corresponding to the local cache slot is only accessible by processors on a same one of the directors as the portion of the memory.

16. A non-transitory computer readable medium, according to claim 11 , wherein following loading the data into the local cache slot, storage of the data in the global cache slot is cancelled.

17. A non-transitory computer readable medium, according to claim 11 , wherein the data from the local cache slot is provided to the specific processor independent of completing modifying system metadata indicating that the data has been loaded into the local cache slot.

18. A non-transitory computer readable medium, according to claim 11 , wherein prior to loading the data in to the local cache slot, prior data is removed from the local cache slot.

19. A non-transitory computer readable medium, according to claim 18 , wherein removing the prior data includes initiating a metadata modification corresponding thereto, wherein the prior data is removed independent of completion of modification of the metadata.

20. A method, according to claim 11 , wherein prior to converting the local cache slot into a global cache slot, the local cache slot is chosen from a plurality of local cache slots that contain the data.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (046366/0014) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060450/0306 →
RELEASE OF SECURITY INTEREST AT REEL 046286 FRAME 0653 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058298/0093 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 046286/0653 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 046366/0014 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2018
From: KHAMBAM, VENKATA; NELSON, JEFFREY R.; ASSELIN, BRIAN; YU, RONG
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 045652/0146 →