Transmit and receive switch and broadband power amplifier matching network for multi-band millimeter-wave 5G communication
View Patent ↗According to one embodiment, a transmit/receive (T/R) switch includes a transmit switch, between a transmit port and an antenna port, a receive switch, between a receive port and the antenna port, a transmit inductor, coupled in parallel between the transmit switch the transmit port, and a receive inductor, coupled in parallel between the transmit switch the transmit port. The T/R switch can be co-designed with a power amplifier (PA) output matching circuit.
1. An electronic circuit for wireless communication, comprising:
a transmit/receive (T/R) switch, the T/R switch including:
a transmit switch, between a transmit port and an antenna port;
a receive switch, between a receive port and the antenna port;
a transmit inductor, coupled in parallel between the transmit switch and the transmit port; and
a receive inductor, coupled in parallel between the receive switch and the receive port, wherein the transmit and receive switches each include two poles, wherein
in an “on” position
a first pole is closed, connecting a respective port to the antenna port,
a second pole is open, disconnecting a respective port to a common return, and
in an “off” position
the first pole is open, disconnecting the respective port from the antenna port, and
the second pole is closed, connecting the respective port to the common return.
2. The electronic circuit for wireless communication, of claim 1 , wherein the transmit inductor has an inductance to resonate out a parasitic capacitance from the transmit switch and the receive inductor has an inductance to resonate out a parasitic capacitance of the receive switch.
3. The electronic circuit of claim 1 , wherein the transmit and receive switches each include one or more field effect transistors.
4. An electronic circuit for wireless communication, comprising
a transmit/receive (T/R) switch, the T/R switch including:
a transmit switch, between a transmit port and an antenna port,
a receive switch, between a receive port and the antenna port,
a transmit inductor, coupled in parallel between the transmit switch and the transmit port, and
a receive inductor, coupled in parallel between the receive switch and the receive port;
a power amplifier (PA) output matching network having a first capacitor coupled, in parallel, to an input port of the matching network circuit;
a broadband on-chip transformer coupled, in parallel, to the first capacitor; and
a second capacitor coupled, in series, in between the broadband on-chip transformer and an output port of the matching network circuit, wherein the output port of the matching network circuit is coupled to the transmit port of the T/R switch.
5. The electronic circuit of claim 4 , wherein a combination of the first capacitor, the on-chip transformer, the second capacitor of the matching circuit, and the transmit inductor and the receive inductor of the T/R switch, results in
a real impedance of the electronic circuit substantially equal to an optimal resistance R OPT at the input port of the PA output matching network,
an imaginary impedance of the circuit substantially equal to zero, and
a low insertion loss.
6. The electronic circuit of claim 4 , wherein the T/R switch and the PA output matching network are a co-designed circuit, the first and second capacitors, transmit inductor, and transformer parameters, have a broadband impedance matched to
a load impedance of an antenna,
an on-resistance of the transmit switch, and
an off-capacitance of the transmit switch.
7. The electronic circuit of claim 4 , wherein the PA output matching network and the T/R switch are an integrated circuit.
8. The electronic circuit of claim 4 , wherein the transmit switch has an “on” state that connects the transmit port to an antenna, and an “off” state that disconnects the transmit port from the antenna.
9. The electronic circuit of claim 4 , wherein the receive switch has an “on” state that connects the receive port to an antenna, and an “off” state that disconnects the receive port from the antenna.
10. The electronic circuit of claim 4 , wherein the transmit and receive switches each include two poles, wherein
in an “on” position
a first pole is closed, connecting a respective port to the antenna port,
a second pole is open, disconnecting a respective port to a common return, and in an “off” position
the first pole is open, disconnecting the respective port from the antenna port, and
the second pole is closed, connecting the respective port to the common return.
11. A radio frequency (RF) front end circuit, comprising:
a transmit/receive (T/R) switch, the T/R switch including:
a transmit switch, between a transmit port and an antenna port;
a receive switch, between a receive port and the antenna port;
a transmit inductor, coupled in parallel between the transmit switch and the transmit port; and
a receive inductor, coupled in parallel between the receive switch and the receive port, wherein the transmit and receive switches each include two poles, wherein
in an “on” position
a first pole is closed, connecting a respective port to the antenna port,
a second pole is open, disconnecting a respective port to a common return, and
in an “off” position
the first pole is open, disconnecting the respective port from the antenna port, and
the second pole is closed, connecting the respective port to the common return.
12. The RF front end circuit of claim 11 , wherein the transmit inductor has an inductance to resonate out a parasitic capacitance from the transmit switch and the receive inductor has an inductance to resonate out a parasitic capacitance of the receive switch.
13. The RF front end circuit of claim 11 , wherein the transmit and receive switches each include one or more field effect transistors.
14. A radio frequency (RF) front end circuit, comprising
a transmit/receive (T/R) switch, the T/R switch including:
a transmit switch, between a transmit port and an antenna port,
a receive switch, between a receive port and the antenna port,
a transmit inductor, coupled in parallel between the transmit switch and the transmit port, and
a receive inductor, coupled in parallel between the receive switch and the receive port;
a power amplifier (PA) output matching network, having a first capacitor coupled, in parallel, to an input port of the matching network circuit;
a broadband on-chip transformer coupled, in parallel, to the first capacitor; and
a second capacitor coupled, in series, in between the broadband on-chip transformer and an output port of the matching network circuit, wherein the output port of the matching network circuit is coupled to the transmit port of the T/R switch.
15. The RF front end circuit of claim 14 , wherein a combination of the first capacitor, the on-chip transformer, the second capacitor of the matching circuit, and the transmit inductor and the receive inductor of the T/R switch, results in
a real impedance of the electronic circuit substantially equal to an optimal resistance R OPT at the input port of the PA output matching network,
an imaginary impedance of the circuit substantially equal to zero, and
a low insertion loss.
16. The RF front end circuit of claim 14 , wherein the T/R switch and the PA output matching network are a co-designed circuit, the first and second capacitors, transmit inductor, and transformer parameters, have a broadband impedance matched to
a load impedance of an antenna,
an on-resistance of the transmit switch, and
an off-capacitance of the transmit switch.
17. The RF front end circuit of claim 14 , wherein the PA output matching network and the T/R switch are an integrated circuit.
18. The RF front end circuit of claim 14 , wherein the transmit switch has an “on” state that connects the transmit port to an antenna, and an “off” state that disconnects the transmit port from the antenna.
19. The RF front end circuit of claim 14 , wherein the receive switch has an “on” state that connects the receive port to an antenna, and an “off” state that disconnects the receive port from the antenna.
20. The RF front end circuit of claim 14 , wherein the transmit and receive switches each include two poles, wherein
in an “on” position
a first pole is closed, connecting a respective port to the antenna port,
a second pole is open, disconnecting a respective port to a common return, and in an “off” position
the first pole is open, disconnecting the respective port from the antenna port, and
the second pole is closed, connecting the respective port to the common return.