IP Library Granted Patent US 10,355,653
Granted Patent B2
US 10,355,653 · App. 15/967,914 · Granted Jul 16, 2019

Power amplifier circuit

Inventor: Hideyuki Sato (Kyoto, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H03F3/213H03F1/083H03F1/302H03F3/195H03F2200/18H03F2200/21H03F2200/222H03F2200/267H03F2200/297H03F2200/451H03G3/3042
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Quick Facts
Patent No.
US 10,355,653
App. No.
15/967,914
Granted
Jul 16, 2019
Kind
B2
Abstract

A power amplifier circuit includes a first amplifier transistor, an input signal being supplied to a base of the first amplifier transistor, a first amplification signal obtained by amplifying the input signal being output from a collector of the first amplifier transistor; a first bias circuit that supplies a first current or a first voltage to the base of the first amplifier transistor; a second bias circuit that supplies a second current or a second voltage to the base of the first amplifier transistor; and a first resistor element that is connected in series between the base of the first amplifier transistor and the first bias circuit. The second bias circuit includes a diode, an impedance circuit, and a first capacitor element.

Claims (57)

1. A power amplifier circuit comprising:

a first amplifier transistor, wherein an input signal is supplied to a base of the first amplifier transistor, and a first amplification signal is obtained by amplifying the input signal and is output from a collector of the first amplifier transistor;

a first bias circuit configured to supply a first current or a first voltage to the base of the first amplifier transistor;

a second bias circuit configured to supply a second current or a second voltage to the base of the first amplifier transistor; and

a first resistor connected in series between the base of the first amplifier transistor and the first bias circuit,

wherein the second bias circuit comprises:

a diode element, wherein a power supply voltage is supplied to an anode of the diode,

an impedance circuit connected between a cathode of the diode element and ground, and

a first capacitor, wherein a first end of the first capacitor is connected to a node between the cathode of the diode element and the impedance circuit, and the second current or the second voltage is supplied from a second end of the first capacitor to the base of the first amplifier transistor.

2. The power amplifier circuit according to claim 1 ,

wherein the diode element comprises a transistor, and

wherein the power supply voltage is supplied to a collector of the transistor, a base of the transistor is connected to the collector of the transistor, and an emitter of the transistor is connected to the impedance circuit.

3. The power amplifier circuit according to claim 1 , further comprising:

a second capacitor connected in series between an input terminal of the power amplification circuit and the base of the first amplifier transistor,

wherein the second end of the first capacitor is connected between the input terminal and the second capacitor.

4. The power amplifier circuit according to claim 2 , further comprising:

a second capacitor connected in series between an input terminal of the power amplification circuit and the base of the first amplifier transistor,

wherein the second end of the first capacitor is connected between the input terminal and the second capacitor.

5. The power amplifier circuit according to claim 1 ,

wherein the impedance circuit comprises a second resistor, wherein a first end of the second resistor is connected to the cathode of the diode and a second end of the second resistor is connected to ground.

6. The power amplifier circuit according to claim 2 ,

wherein the impedance circuit comprises a second resistor, wherein a first end of the second resistor is connected to the cathode of the diode and a second end of the second resistor is connected to ground.

7. The power amplifier circuit according to claim 3 ,

wherein the impedance circuit comprises a second resistor, wherein a first end of the second resistor is connected to the cathode of the diode and a second end of the second resistor is connected to ground.

8. The power amplifier circuit according to claim 1 ,

wherein the impedance circuit comprises a variable resistor, a resistance of the variable resistor being adjusted according to at least one of a communication standard of the input signal and a frequency band of the input signal.

9. The power amplifier circuit according to claim 2 ,

wherein the impedance circuit comprises a variable resistor, a resistance of the variable resistor being adjusted according to at least one of a communication standard of the input signal and a frequency band of the input signal.

10. The power amplifier circuit according to claim 3 ,

wherein the impedance circuit comprises a variable resistor, a resistance of the variable resistor being adjusted according to at least one of a communication standard of the input signal and a frequency band of the input signal.

11. The power amplifier circuit according to claim 8 ,

wherein the first amplifier transistor, the first bias circuit, the first resistor, the diode element, and the first capacitor are formed on a heterojunction bipolar transistor chip, and

wherein the variable resistor is formed on a chip other than the heterojunction bipolar transistor chip.

12. The power amplifier circuit according to claim 8 ,

wherein the variable resistor is formed on a control integrated circuit configured to output a signal, and

wherein the resistance of the variable resistor is configured to be adjusted based on the signal.

13. The power amplifier circuit according to claim 8 ,

wherein the variable resistor comprises a plurality of resistors connected in parallel with each other, and

wherein all but one of the plurality of resistors is selectively connected to ground.

14. The power amplifier circuit according to claim 13 ,

wherein the second end of the first capacitor is connected directly to the base of the first amplifier transistor.

15. The power amplifier circuit according to claim 1 , further comprising:

a second amplifier transistor, wherein the first amplification signal is supplied to a base of the second amplifier transistor, and a second amplification signal is obtained by amplifying the first amplification signal and is output from a collector of the second amplifier transistor;

a third bias circuit configured to supply a third current or a third voltage to the base of the second amplifier transistor; and

a third resistor connected in series between the base of the second amplifier transistor and the third bias circuit.

16. The power amplifier circuit according to claim 2 , further comprising:

a second amplifier transistor, wherein the first amplification signal is supplied to a base of the second amplifier transistor, and a second amplification signal is obtained by amplifying the first amplification signal and is output from a collector of the second amplifier transistor;

a third bias circuit configured to supply a third current or a third voltage to the base of the second amplifier transistor; and

a third resistor connected in series between the base of the second amplifier transistor and the third bias circuit.

17. The power amplifier circuit according to claim 3 , further comprising:

a second amplifier transistor, wherein the first amplification signal is supplied to a base of the second amplifier transistor, and a second amplification signal is obtained by amplifying the first amplification signal and is output from a collector of the second amplifier transistor;

a third bias circuit configured to supply a third current or a third voltage to the base of the second amplifier transistor; and

a third resistor connected in series between the base of the second amplifier transistor and the third bias circuit.

18. The power amplifier circuit according to claim 5 , further comprising:

a second amplifier transistor, wherein the first amplification signal is supplied to a base of the second amplifier transistor, and a second amplification signal is obtained by amplifying the first amplification signal and is output from a collector of the second amplifier transistor;

a third bias circuit configured to supply a third current or a third voltage to the base of the second amplifier transistor; and

a third resistor connected in series between the base of the second amplifier transistor and the third bias circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2018
From: SATO, HIDEYUKI
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 045859/0460 →
Priority Claims (1)
JP 2017-101540 · May 23, 2017 · national
Continuity (1)
Related Publication 20180342992A1 · Nov 29, 2018