Techniques for improving space utilization in a cache
A system and method for efficient cache space utilization by a processing circuitry having a cache. The method includes determining, among a plurality of instructions executed by the processing circuitry, a cacheable block of instructions for execution by the processing circuitry, wherein the cacheable block of instructions has an input, an output, and an intermediary result confined locally to the cacheable block of instructions; generating a unified instruction based on the cacheable block of instructions, wherein the unified instruction results in the same output as the cacheable block of instructions when the same input is received; and storing the unified instruction in the cache.
1. A method for efficient cache space utilization by a processing circuitry including a cache, the method comprising:
determining whether a number of executions of a first instruction is at or above a first threshold, wherein the first threshold is at least 2;
determining whether a number of executions of a second instruction is at or above a second threshold when it is determined that the number of executions of the first instruction is at or above the first threshold;
determining, among a plurality of instructions executed by the processing circuitry, a cacheable block of instructions for execution by the processing circuitry, wherein the cacheable block of instructions has an input, an output, and an intermediary result confined locally to the cacheable block of instructions, wherein the cacheable block of instructions includes the first instruction and the second instruction when it is determined that the number of executions of the first instruction is at or above the first threshold and that the number of executions of the second instruction is at or above the second threshold, wherein the first instruction generates the intermediary result based on the input, wherein the second instruction generates the output based on the intermediary result;
generating a unified instruction based on the cacheable block of instructions, wherein the unified instruction results in the same output as the cacheable block of instructions when the same input is received; and
storing the unified instruction in the cache.
2. The method of claim 1 , wherein the unified instruction is stored in the cache for a predetermined amount of time.
3. The method of claim 1 , wherein the unified instruction is removed from the cache when it is determined that a number of executions of the unified instruction is below a predetermined threshold for a period of time.
4. The method of claim 1 , wherein determining the cacheable block of instructions further comprises:
identifying a potentially cacheable block of instructions including the first instruction, the second instruction, and the intermediary result of the first instruction used by the second instruction that is locally confined to the identified block of instructions.
5. The method of claim 4 , wherein the identified block of instructions is determined to be cacheable when the number of executions of the first instruction is at or above the first threshold.
6. The method of claim 4 , wherein the identified block of instructions is determined to be cacheable when the number of executions of the second instruction is at or above the second threshold.
7. The method of claim 4 , wherein the identified block of instructions is determined to be cacheable when the number of executions of the first instruction is above the first threshold and the number of executions of the second instruction is at or above the second threshold.
8. The method of claim 1 , wherein the plurality of instructions is performed on a columnar database.
9. The method of claim 1 , wherein the first threshold is different from the second threshold.
10. A non-transitory computer readable medium having stored thereon instructions for causing a processor to execute a process for efficient cache space utilization by a processing circuitry including a cache, the process comprising:
determining whether a number of executions of a first instruction is at or above a first threshold, wherein the first threshold is at least 2;
determining whether a number of executions of a second instruction is above a second threshold when it is determined that the number of executions of the first instruction is at or above the first threshold;
determining, among a plurality of instructions executed by the processing circuitry, a cacheable block of instructions for execution by the processing circuitry, wherein the cacheable block of instructions has an input, an output, and an intermediary result confined locally to the cacheable block of instructions, wherein the cacheable block of instructions includes the first instruction and the second instruction when it is determined that the number of executions of the first instruction is at or above the first threshold and that the number of executions of the second instruction is at or above the second threshold, wherein the first instruction generates the intermediary result based on the input, wherein the second instruction generates the output based on the intermediary result;
generating a unified instruction based on the cacheable block of instructions, wherein the unified instruction results in the same output as the cacheable block of instructions when the same input is received; and
storing the unified instruction in the cache.
11. A system for efficient cache space utilization, comprising:
a processing circuitry including a cache, wherein the processing circuitry is configured to execute at least a plurality of instructions; and
a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:
determine whether a number of executions of a first instruction is at or above a first threshold, wherein the first threshold is at least 2;
determine whether a number of executions of a second instruction is at or above a second threshold when it is determined that the number of executions of the first instruction is at or above the first threshold;
determine, among a plurality of instructions executed by the processing circuitry, a cacheable block of instructions for execution by the processing circuitry, wherein the cacheable block of instructions has an input, an output, and an intermediary result confined locally to the cacheable block of instructions, wherein the cacheable block of instructions includes the first instruction and the second instruction when it is determined that the number of executions of the first instruction is at or above the first threshold and that the number of executions of the second instruction is at or above the second threshold, wherein the first instruction generates the intermediary result based on the input, wherein the second instruction generates the output based on the intermediary result;
generate a unified instruction based on the cacheable block of instructions, wherein the unified instruction results in the same output as the cacheable block of instructions when the same input is received; and
store the unified instruction in the cache.
12. The system of claim 11 , wherein the unified instruction is stored in the cache for a predetermined amount of time.
13. The system of claim 11 , wherein the unified instruction is removed from the cache when it is determined that a number of executions of the unified instruction is below a predetermined threshold for a period of time.
14. The system of claim 11 , wherein the system is further configured to:
identify a potentially cacheable block of instructions including the first instruction, the second instruction, and the intermediary result of the first instruction used by the second instruction that is locally confined to the identified block of instructions.
15. The system of claim 14 , wherein the identified block of instructions is determined to be cacheable when the number of executions of the first instruction is at or above the first threshold.
16. The system of claim 14 , wherein the identified block of instructions is determined to be cacheable when the number of executions of the second instruction is at or above the second threshold.
17. The system of claim 14 , wherein the identified block of instructions is determined to be cacheable when the number of executions of the first instruction is at or above the first threshold and the number of executions of the second instruction is at or above the second threshold.
18. The system of claim 11 , wherein the plurality of instructions is performed on a columnar database.