Storage system with data durability signaling for directly-addressable storage devices
View Patent ↗A storage system in one embodiment comprises at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory. The input-output controller generates a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts. If an address of a given one of the write commands falls within a specified interrupt group window, the write command is copied to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device. The directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor.
1. A storage system comprising:
at least one processor;
a processor memory;
an input-output controller; and
a directly-addressable storage device having volatile memory and non-volatile memory;
wherein the input-output controller generates a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts;
wherein the storage system is configured:
to determine which of first and second windows that an address of a given one of the write commands falls within;
responsive to the address falling within the first window, to write the data to the processor memory and to copy the write command to the directly-addressable storage device so as to cause the data to also be written to the volatile memory of that storage device; and
responsive to the address falling within the second window, to copy the write command to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device.
2. The storage system of claim 1 wherein the processor further comprises a PCIe root complex having a plurality of root ports supporting communication with the input-output controller and the directly-addressable storage device.
3. The storage system of claim 2 further comprising a PCIe switch coupled via an upstream port of the PCIe switch to a given one of the root ports of the PCIe root complex of the processor and coupled via respective downstream ports of the PCIe switch to the input-output controller and the directly-addressable storage device.
4. The storage system of claim 3 wherein the PCIe switch further comprises multicast logic configured to determine if the address of the given write command falls within a specified data group window or a specified interrupt group window and to control copying of the write command in accordance with that determination.
5. The storage system of claim 1 wherein the write commands comprise respective PCIe writes.
6. The storage system of claim 1 wherein the directly-addressable storage device comprises one or more solid-state drives.
7. The storage system of claim 1 wherein the interrupt provided to the directly-addressable storage device is interpreted by the directly-addressable storage device as a request to commit any outstanding data in the volatile memory to the non-volatile memory.
8. The storage system of claim 1 wherein the directly-addressable storage device comprises at least one programmable base address register.
9. The storage system of claim 8 wherein the directly-addressable storage device confirms that the interrupt provided to the directly-addressable storage device falls within a range of a predefined base address register prior to responding to receipt of the interrupt.
10. The storage system of claim 1 wherein the directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor, and wherein the interrupt to the processor provides an acknowledgment from the directly-addressable storage device to the processor that any outstanding data in the volatile memory has been committed to the non-volatile memory.
11. The storage system of claim 1 wherein the directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor, and wherein the interrupt to the processor comprises a modified version of the interrupt provided to the directly-addressable storage device.
12. The storage system of claim 1 wherein the directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor, and wherein the interrupt to the processor comprises a unique interrupt that is distinct from the interrupt provided to the directly-addressable storage device.
13. The storage system of claim 1 wherein the interrupts comprise respective message signaled interrupts.
14. An information processing system comprising the storage system of claim 1 and one or more additional devices that provide the data to the input-output controller.
15. A method comprising:
configuring a storage system to include at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory;
generating in the input-output controller a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts;
determining which of first and second windows that an address of a given one of the write commands falls within;
responsive to the address falling within the first window, writing the data to the processor memory and copying the write command to the directly-addressable storage device so as to cause the data to also be written to the volatile memory of that storage device; and
responsive to the address falling within the second window, copying the write command to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device.
16. The method of claim 15 wherein the storage system further comprises a PCIe switch coupled via an upstream port of the PCIe switch to a root port of a PCIe root complex of the processor and coupled via respective downstream ports of the PCIe switch to the input-output controller and the directly-addressable storage device.
17. The method of claim 16 wherein the PCIe switch further comprises multicast logic configured to determine if the address of the given write command falls within a specified data group window or a specified interrupt group window and to control copying of the write command in accordance with that determination.
18. A computer program product comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code, when executed by a storage system comprising at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory, causes the storage system:
to generate in the input-output controller a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts;
to determine which of first and second windows that an address of a given one of the write commands falls within;
responsive to the address falling within the first window, to write the data to the processor memory and to copy the write command to the directly-addressable storage device so as to cause the data to also be written to the volatile memory of that storage device; and
responsive to the address falling within the second window, to copy the write command to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device.
19. The computer program product of claim 18 wherein the storage system further comprises a PCIe switch coupled via an upstream port of the PCIe switch to a root port of a PCIe root complex of the processor and coupled via respective downstream ports of the PCIe switch to the input-output controller and the directly-addressable storage device.
20. The computer program product of claim 19 wherein the PCIe switch further comprises multicast logic configured to determine if the address of the given write command falls within a specified data group window or a specified interrupt group window and to control copying of the write command in accordance with that determination.