Built-in self test for loopback on communication system on chip

1. An integrated system-on-chip photonics module for optical network, the module comprising:

a substrate member made by silicon;

a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol;

an input/output block provided on the substrate member and coupled or the data input/output interface, the input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block;

a signal processing block provided on the substrate member and coupled to the input/output block, the signal processing block configured to the input/output block using a bi-direction bus in an intermediary protocol;

a driver module provided on the substrate member and coupled to the signal processing block using a uni-directional multi-lane bus;

a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device, the driver interface being configured to transmit output data in either an amplitude modulation format or a combination of phase/amplitude modulation format or a phase modulation format;

a receiver module comprising a TIA block provided on the substrate member and to be coupled to the silicon photonics device using predefined modulation format, and configured to the signal processing block to communicate information to the input/output block for transmission through the data input/output interface;

a laser coupled to the silicon photonics device;

a communication block provided on the substrate member and operably coupled to the input/output block, the signal processing block, the driver block, and the receiver block;

a communication interface coupled to the communication block;

a control block provided on the substrate member and coupled to the communication block; and

a self-test block provided on the substrate member, the self test block comprising a broad band source coupled to each of a TX multiplexer and a RX multiplexer associated with the silicon photonics device and a self test output configured to couple to an external spectrum analyzer, and being configured to receive a loop back signal from at least one of the digital signal processing block, the driver module, or the silicon photonics device under a loop back control based on locking individual wavelengths to N channels of an N-to-1 multiplexer.

2. The module of claim 1 wherein the signal processing block comprises a FEC block, a digital signal processing block, a framing block, a protocol block, and a redundancy block.

3. The module of claim 1 wherein the driver module is selected from a current driver or a voltage driver.

4. The module of claim 1 wherein the driver module is a differential driver.

5. The module of claim 1 wherein the driver module comprises N lasers to generate the N channels of individual wavelengths, wherein the N lasers are controlled by thermo-electric tuners and a phase modulation controller before processed by an electro absorption modulator using either DC or RF control signals, each laser being associated with a different wavelength locked by the loop back control using a detected error signal by a photo detector in the external spectrum analyzer from a taped signal based on the self-test output from the N-to-1 multiplexer.

6. The module of claim 1 wherein the silicon photonics device is selected from an electro absorption modulator or electro optic modulator, or a Mach-Zehnder modulator.

7. The module of claim 1 wherein the amplified modulation format is selected from NRZ format or PAM format.

8. The module of claim 1 wherein the phase modulation format is selected from BPSK or nPSK.

9. The module of claim 1 wherein the phase/amplitude modulation is QAM.

10. The module of claim 1 wherein the silicon photonic device is configured to convert the output data into an output transport data in a WDM signal.

11. The module of claim 1 wherein the control block is configured to initiate a laser bias or a modulator bias.

12. The module of claim 1 wherein the control block is configured for laser bias and power control of the silicon photonics device.

13. The module of claim 1 wherein the control block is configured with a thermo-electric tuning or carrier tuning device each of which is configured on the silicon photonics device.

14. The module of claim 1 wherein the SerDes block is configured to convert a first N numbers of data streams into a second M numbers of data streams.

15. The module of claim 1 wherein the self test block comprises a variable output power switch configured to provide a receiver stress test from the loop back signal.

16. The module of claim 5 wherein the DC control signal is to set an operating point per channel and the RF control signal is to generate a dither for locking the operating point, wherein the error signal is deduced by demolulating the dither detected by the photo detector in the external spectrum analyzer.

17. The module of claim 16 wherein the dither and the error signal can be applied by itself or by a derivative signal as an input of the loop back control to lock to a null condition to establish a correct operating point by changing bias points of the thermo-electric tuners and the phase modulation controller.

18. The module of claim 17 wherein the RF control signal comprises different frequency for different channel using a frequency division multiplexed approach.

19. The module of claim 17 wherein the dither is cycling its frequency values through each channel to demodulated during a respective divisional time period in a time division multiplexed approach.

20. The module of claim 1 wherein the loop back control is executed as a cascaded control such that a first control current signal of a first loop tracks a laser phase control, and a second control current signal of a second loop then tracks the first control current signal of the first loop with data signals being processed in parallel.