IP Library › Patent Application 15975761

Patent Application

App. No. 15/975,761

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

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Patent No.: US None
App. No.: 15/975,761

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Abstract

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW 1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Claims (110)

1 - 29 . (canceled)

30 . A semiconductor memory device comprising:

first and second bit lines extending in a first direction;

a plurality of word lines extending in a second direction crossing the first direction;

a memory array having a plurality of memory cells, each of the memory cells having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal of the second inverter being coupled to an output terminal of the first inverter and with an output terminal of the second inverter being coupled to an input terminal of the first inverter, a third N-channel MOS transistor having a source/drain path coupled between the output terminal of the first inverter and the first bit line, and a fourth N-channel MOS transistor having a source/drain path coupled between the output terminal of the second inverter and the second bit line, a gate of each of the third and fourth N-channel MOS transistors being connected to one of the plurality of word lines;

a first P-type well region in which the first and third N-channel MOS transistors are formed and which is formed commonly throughout the plurality of memory cells, the first P-type well region extending in the first direction;

a second P-type well region in which the second and fourth N-channel MOS transistors are formed and which is formed commonly throughout the plurality of memory cells, the second P-type well region extending in the first direction; and

an N-type well region in which the first and second P-channel MOS transistors are formed and which is formed commonly throughout the plurality of memory cells, the N-type well region lying between the first and second P-type well regions;

wherein with respect to a plan view of a principal plane of the semiconductor memory device,

(i) each of the plurality of memory cells is formed in a rectangular region which includes the first to fourth N-channel MOS transistors, the first and second P-channel MOS transistors, a first contact coupled between the third N-channel MOS transistor and the first bit line, a second contact coupled between the fourth N-channel MOS transistor and the second bit line, a third contact coupled between one of the plurality of word lines and the gate of the third N-channel MOS transistor, and a fourth contact coupled between the one of the plurality of word lines and the gate of the fourth N-channel MOS transistor,

(ii) the memory array has a first area which consists of plural rectangular regions arranged in the first direction,

(iii) a second area in which a first well contact to the first P-type well region is arranged without being overlapped with the first area,

(iv) a third area in which a second well contact to the first P-type well region is arranged without being overlapped with the first area, and

wherein the first P-type well region in the first area is supplied with a first voltage from the second area and the third area, and the first area has no contact to supply the first voltage to the first P-type well region,

wherein, in the plan view, no memory cell is formed in the second area and no memory cell is formed in the third area, and

wherein a first well contact arranged in the second area and a second well contact arranged in the third area are disposed at upper and lower portions of the memory array, respectively.

31 . The semiconductor memory device according to claim 30 ,

wherein the memory array has

(v) a fourth area in which a third well contact to the second P-type well region is arranged without being overlapped with the first area, and

(vi) a fifth area in which a fourth well contact to the second P-type well region is arranged without being overlapped with the first area,

wherein the second P-type well region in the first area is supplied with the first voltage from the fourth area and the fifth area, and the first area has no contact to supply the first voltage to the second P-type well region, and

wherein, in the plan view, no memory cell is formed in the fourth area and no memory cell is formed in the fifth area.

32 . The semiconductor memory device according to claim 31 , further comprising:

a first electrical lead to supply the first voltage to the first and second P-type well regions via the first well contact and the third well contact, respectively; and

a second electrical lead to supply the first voltage to the first and second P-type well regions via the second well contact and the well fourth contact, respectively,

wherein the first and second electrical leads extend in the second direction.

33 . The semiconductor memory device according to claim 32 ,

wherein the first and third well contacts are linearly disposed in the second direction, and

wherein the second and fourth well contacts are linearly disposed in the second direction.

34 . The semiconductor memory device according to claim 31 ,

wherein the memory array has

(vii) a sixth area in which a fifth well contact to the N-type well region is arranged without being overlapped with the first area, and

(viii) a seventh area in which a sixth well contact to the N-type well region is arranged without being overlapped with the first area, and

wherein the N-type well region in the first area is supplied with a second voltage from the sixth area and the seventh area, and the first area has no contact to supply the second voltage to the N-type well region.

35 . The semiconductor memory device according to claim 31 , further comprising a sense amplifier,

wherein the third and the fifth areas are arranged between the first area and the sense amplifier.

36 . A semiconductor memory device comprising:

first and second bit lines extending in a first direction;

a plurality of word lines extending in a second direction crossing the first direction;

and

wherein with respect to a plan view of a principal plane of the semiconductor memory device,

(ii) the memory array has a first area which consists of plural rectangular regions arranged in a first direction,

(iii) a second area in which a first well contact to the first P-type well region is arranged without being overlapped with the first area,

(iv) a third area in which a second well contact to the second P-type well region is arranged without being overlapped with the first area, and

wherein the first P-type well region in the first area is supplied with a first voltage from the second area, the second P-type well region in the first area is supplied with the first voltage from the third area, and the first area has no contact to supply the first voltage to the first P-type well region and has no contact to supply the first voltage to the second P-type well region,

wherein, in the plan view, no memory cell is formed in the second area and no memory cell is formed in the third area, and

wherein a first well contact arranged in the second area and a second well contact arranged in the third area are linearly disposed at one of an upper portion and a lower portion of the memory array in the second direction.

37 . The semiconductor memory device according to claim 36 , further comprising:

a first electrical lead to supply the first voltage to the first and second P-type well regions via the first contact and the second contact, respectively; and

wherein the first electrical lead extends in the second direction.

38 . The semiconductor memory device according to claim 37 ,

wherein the first and second well contacts are linearly disposed in the second direction.

39 . The semiconductor memory device according to claim 36 , further comprising a sense amplifier,

wherein the second and third areas are arranged between the first area and the sense amplifier.

40 . A semiconductor memory device comprising:

a pair of bit lines extending in a first direction;

a plurality of word lines extending in a second direction crossing the first direction;

a first memory array and a second memory array each having a plurality of memory cells, each of the memory cells having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal of the second inverter being coupled to an output terminal of the first inverter and with an output terminal of the second inverter being coupled to an input terminal of the first inverter, a third N-channel MOS transistor having a source/drain path coupled between the output terminal of the first inverter and one of the pair of bit lines, and a fourth N-channel MOS transistor having a source/drain path coupled between the output terminal of the second inverter and the other of the pair of bit lines, a gate of each of the third and fourth N-channel MOS transistors being connected to one of the plurality of word lines;

a first electrical lead to supply a first voltage to the first and second P-type well regions; and

a second electrical lead to supply a second voltage to the N-type well region,

wherein the first memory array includes a first memory cell and the second memory array includes a second memory cell,

wherein the plurality of word lines includes a first and word line and a second word line,

wherein with respect to a plan view of a principal plane of the semiconductor memory device,

(i) the first memory cell is formed in a first rectangular region defined by a first and a second side extending in the second direction and a fifth and a sixth side extending in the first direction,

(ii) the second memory cell is formed in a second rectangular region defined by a third and a fourth side extending in the second direction and a seventh and an eighth side extending in the first direction,

(iii) a third rectangular region bounded by the second and third sides is formed between the first and second memory arrays, the first electrical lead being electrically connected with the first and second P-type well regions in the third rectangular region, and the second electrical lead being electrically connected with the N-type well region in the third rectangular region,

(iv) a first contact coupled between the third N-channel MOS transistor of the first memory cell and the one of the pair of bit lines is arranged on the first side, a second contact coupled between the fourth N-channel MOS transistor of the first memory cell and the other of the pair of bit lines is arranged on the second side, a third contact coupled between a first of the word lines and the gate of the third N-channel MOS transistor of the first memory cell is arranged on the fifth side, and a fourth contact coupled between the first word line and the gate of the fourth N-channel MOS transistor of the first memory cell is arranged on the sixth side,

(v) a fifth contact coupled between the third N-channel MOS transistor of the second memory cell and the one of the pair of bit lines is arranged on the fourth side, a sixth contact coupled between the fourth N-channel MOS transistor of the second memory cell and the other of the pair of bit lines is arranged on the third side, a seventh contact coupled between a second of the word lines and the gate of the third N-channel MOS transistor of the second memory cell is arranged on the seventh side, and an eighth contact coupled between the second word line and the gate of the fourth N-channel MOS transistor of the second memory cell is arranged on the eighth side,

wherein the first P-type well region in the first and second memory arrays is supplied with the first voltage from the third rectangular region, and each of the first and second memory arrays has no contact to supply the first voltage to the first P-type well region,

wherein, in the plan view, no memory cell is formed in the third rectangular region,

wherein the second P-type well region in the first and second memory arrays is supplied with the first voltage from the third rectangular region, and each of the first and second memory arrays has no contact to supply the first voltage to the second P-type well region, and

wherein the N-type well region in the first and second memory arrays is supplied with the second voltage from the third rectangular region, and each of the first and second memory arrays has no contact to supply the second voltage to the N-type well region.

41 . The semiconductor memory device according to claim 40 ,

wherein the pair of bit lines includes a first bit line and a second bit line,

wherein the source/drain path of the third N-channel MOS transistor is coupled between the output terminal of the first inverter and the first bit line,

wherein the source/drain path of the fourth N-channel MOS transistor is coupled between the output terminal of the second inverter and the second bit line,

wherein the first contact is coupled between the third N-channel MOS transistor of the first memory cell and the first bit line,

wherein the second contact is coupled between the fourth N-channel MOS transistor of the first memory cell and the second bit line,

wherein the fifth contact is coupled between the third N-channel MOS transistor of the second memory cell and first bit line, and

wherein the sixth contact is coupled between the fourth N-channel MOS transistor of the second memory cell and second bit line.

42 . The semiconductor memory device according to claim 41 ,

wherein the first and second electrical leads are parallel to the plurality of word lines.

43 . The semiconductor memory device according to claim 42 ,

wherein the first and second electrical leads and the plurality of word lines are formed in a same layer.

44 . The semiconductor memory device according to claim 42 , further comprising a power supply line and a ground line,

wherein the power supply line is parallel to the first and second bit lines, and

wherein the ground line is parallel to the plurality of word lines.

45 . The semiconductor memory device according to claim 42 ,

wherein the first and second electrical leads are formed in another layer than a layer in which the first and second bit lines are formed.

46 . The semiconductor memory device according to claim 40 ,

wherein the first voltage is a ground potential and the second voltage is a power supply voltage.

47 . The semiconductor memory device according to claim 40 , further comprising a third memory cell arranged adjacent to the first memory cell in the second direction,

a first diffusion layer forms a source of the first and third N-channel MOS transistors of the first memory cell,

a second diffusion layer forms a source of a third and a fourth N-channel MOS transistor of the third memory cell,

wherein the first and second diffusion layers are formed in the first P-type well region;

wherein the first diffusion layer has no contact part to the second diffusion layer.

48 . The semiconductor memory device according to claim 40 ,

wherein the third rectangular region is bounded by ninth and tenth sides joining the second and third sides,

wherein the ninth side is arranged in line with the fifth and seventh sides, and

wherein the tenth side is arranged in line with the sixth and eighth sides.

49 . The semiconductor memory device according to claim 40 ,

wherein each of the first and the second memory arrays includes greater than or equal to 32 memory cells arranged in parallel to the first bit line in plan view.