Rapid side-channel access to storage devices

1. A method comprising:

receiving, by a processor, a data access command, the data access command specifying a host address of a memory to access data;

determining, by the processor, that the data access command is a critical access command based on the content of the data access command;

issuing, by the processor, the data access command to a controller of a storage device via a first datapath, the first datapath comprising a non-block datapath; and

accessing, by the processor, a non-volatile storage component of the storage device through the first datapath and the memory, wherein the non-volatile storage component is mapped to the memory accessible by the processor.

2. The method of claim 1 , the mapping a non-volatile storage component to memory of the storage device to memory accessible by the processor comprising mapping a portion of dynamic random-access memory (DRAM) to memory.

3. The method of claim 2 , the mapping a portion of DRAM to memory comprising mapping the portion of DRAM to memory using a Peripheral Component Interconnect (PCI) base address register (BAR) of the storage device.

4. The method of claim 3 , the mapping a portion of DRAM to memory comprising identifying a size of the portion of DRAM to map, the identifying comprising computing a maximum portion size based on a power loss capacitance supplied to the DRAM.

5. The method of claim 3 , the accessing the non-volatile storage component through the first datapath and the memory comprising accessing the non-volatile storage component as a byte-addressable read cache or a byte-accessible write cache.

6. The method of claim 1 , the accessing the non-volatile storage component through the first datapath and the memory comprising writing journaling data of an underlying data access command to the non-volatile storage component.

7. The method of claim 1 , the mapping a non-volatile storage component to memory the storage device to memory accessible by the processor comprising mapping a portion of a storage class memory (SCM) to the memory.

8. The method of claim 7 , the mapping a portion of an SCM to memory comprising mapping one of a phase change memory (PCM), resistive random-access memory (ReRAM), or spin-transfer torque RAM (STT-RAM) to the memory.

9. The method of claim 7 , the mapping a portion of an SCM to memory comprising mapping the SCM to the memory via a controller memory buffer (CMB) window.

10. The method of claim 1 , further comprising issuing, by the processor, a block-based data access command via a second datapath after receiving a result of accessing the non-volatile storage component through the first datapath.

11. A system comprising:

a storage device, the storage device including a non-volatile storage component;

a processor;

a memory for tangibly storing thereon program logic for execution by the processor, the stored program logic comprising:

logic, executed by the processor, for receiving a data access command, the data access command specifying a host address of a memory to access data;

logic, executed by the processor, for determining that the data access command is a critical access command based on the content of the data access command;

logic, executed by the processor, for issuing the data access command to a controller of the storage device via a first datapath, the first datapath comprising a non-block datapath; and

logic, executed by the processor, for accessing the non-volatile storage component through the first datapath and the memory, wherein the non-volatile storage component of the storage device is mapped to the memory.

12. The system of claim 11 , the logic for mapping the non-volatile storage component to the memory comprising logic, executed by the processor, for mapping a portion of dynamic random-access memory (DRAM) to host memory.

13. The system of claim 12 , the logic for mapping a portion of DRAM to host memory comprising logic, executed by the processor, for mapping the portion of DRAM to memory using a Peripheral Component Interconnect (PCI) base address register (BAR) of the storage device.

14. The system of claim 13 , the logic for mapping a portion of DRAM to host memory comprising identifying a size of the portion of DRAM to map, the identifying comprising computing a maximum portion size based on a power loss capacitance supplied to the DRAM.

15. The system of claim 13 , the logic for accessing the non-volatile storage through the first datapath and the host memory comprising accessing the non-volatile storage component as a byte-addressable read cache or a byte-accessible write cache.

16. The system of claim 11 , the logic for accessing the non-volatile storage component through the first datapath and the host memory comprising logic, executed by the processor, for writing journaling data of an underlying data access command to the non-volatile storage component.

17. The system of claim 11 , the logic for mapping a non-volatile storage component to the memory comprising logic, executed by the processor, for mapping a portion of a storage class memory (SCM) to the host memory.

18. The system of claim 17 , the logic mapping a portion of an SCM to host memory comprising logic, executed by the processor, for mapping one of a phase change memory (PCM), resistive random-access memory (ReRAM), or spin-transfer torque RAM (STT-RAM) to the host memory.

19. The system of claim 17 , the logic for mapping a portion of an SCM to host memory comprising logic, executed by the processor, for mapping the SCM to the host memory via a controller memory buffer (CMB) window.

20. The system of claim 11 , the program logic further comprising logic, executed by the processor, for issuing a block-based data access command via a second datapath after receiving a result of accessing the non-volatile storage component through the first datapath.