MULTILAYER CAPACITOR AND CIRCUIT BOARD CONTAINING THE SAME
The present invention is directed to a multilayer capacitor and a circuit board containing the multilayer capacitor. The capacitor includes a main body containing at least two sets of alternating dielectric layers and internal electrode layers. Each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge that define a main body of the internal electrode layer and contains at least one lead tab extending from the top edge and at least one lead tab extending from the bottom edge. The capacitor includes external terminals electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposing the top surface of the capacitor. The capacitor has an inductance of less than 1 nanohenry.
1 . A multilayer capacitor comprising:
a main body containing a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers,
each set of alternating dielectric layers and internal electrode layers containing a first internal electrode layer and a second internal electrode layer,
each internal electrode layer including a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge that define a main body of the internal electrode layer,
each internal electrode layer containing at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer,
external terminals electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposing the top surface of the capacitor, and
wherein the capacitor has an inductance of less than 1 nanohenry.
2 . The capacitor according to claim 1 , wherein the capacitor has an inductance of less than 10 picohenries.
3 . The capacitor according to claim 1 , wherein the capacitor has an inductance of less than 1 picohenry.
4 . The capacitor according to claim 1 , wherein the first internal electrode layer and the second internal electrode layer are interleaved in an opposed relation and a dielectric layer is positioned between the first internal electrode layer and the second internal electrode layer.
5 . The capacitor according to claim 1 , wherein each internal electrode layer includes at least two lead tabs extending from the top edge, the bottom edge, or both the top edge and the bottom edge.
6 . The capacitor according to claim 1 , wherein at least one lateral edge of the lead tab on the top edge is substantially aligned with at least one lateral edge of the lead tab on the bottom edge.
7 . The capacitor according to claim 1 , wherein at least one lateral edge of the lead tab on the top edge, at least one lateral edge of the lead tab on the bottom edge, or both are aligned with a side edge.
8 . The capacitor according to claim 1 , wherein at least one lateral edge of the lead tab on the top edge and at least one lateral edge of the lead tab on the bottom edge are aligned with the side edge.
9 . The capacitor according to claim 1 , wherein at least one lead tab is offset from the side edge while at least one lead tab is aligned with the side edge wherein at least one of the lead tabs is on the top edge and the other lead tab is on the bottom edge.
10 . The capacitor according to claim 1 , wherein at least one lead tab on the top edge is offset from the side edge a different distance than an offset of at least one lead tab on the bottom edge.
11 . The capacitor according to claim 1 , wherein the top edge and the bottom edge include a different number of lead tabs.
12 . The capacitor according to claim 1 , wherein the external terminals include an electroplated layer.
13 . The capacitor according to claim 1 , wherein the external terminals include an electroless plated layer.
14 . The capacitor according to claim 1 , wherein the external terminals include an electroless plated layer and an electroplated layer.
15 . The capacitor according to claim 1 , wherein the external terminals include a first electroless plated layer, a second electroplated layer, and a third electroplated layer.
16 . The capacitor according to claim 15 , wherein the first electroless plated layer includes copper, the second electroplated layer includes nickel, and the third electroplated layer includes tin.
17 . The capacitor according to claim 1 , wherein the capacitor includes at least three sets of alternating dielectric layers and internal electrode layers.
18 . A circuit board including the capacitor according to claim 1 positioned on the circuit board.
19 . The circuit board according to claim 18 , wherein the board further comprises an integrated circuit package and wherein the capacitor is positioned between the circuit board and the integrated circuit package in a vertical direction such that the circuit board, the capacitor, and the integrated circuit package are present in a stacked arrangement.
20 . The circuit board according to claim 19 , wherein the capacitor is directly connected to the circuit board and the integrated circuit package.
21 . An integrated circuit package containing the capacitor according to claim 1 .