Tamper-proof, dual-boot information handling system having operating system-specific hardware and/or firmware components

1. A method, comprising:

producing, by an Embedded Controller (EC) of an Information Handling System (IHS), a Real-Time Clock (RTC) battery-powered General-Purpose Input/Output (GPIO) control or external latch;

applying the RTC battery-powered GPIO control to a chip select circuit; and

selecting, via the chip select circuit: (i) a first flash memory configured to boot the IHS into a diagnostic mode or first Operating System (OS), or (ii) a second flash memory configured to boot the IHS into a native OS.

2. The method of claim 1 , further comprising holding a security chip in reset using the RTC battery-powered GPIO control while in the diagnostic mode.

3. The method of claim 1 , further comprising using a tamper-proof circuit to allow the selecting to take place before the Central Processing Unit (CPU) is powered on.

4. The method of claim 3 , wherein the tamper-proof circuit is configured to isolate the RTC battery-powered GPIO control from the chip select circuit after booting of the EC.

5. The method of claim 4 , wherein the tamper-proof circuit is configured to maintain a value of the RTC battery-powered GPIO control applied to the chip select circuit in response to tampering with the chip select circuit.

6. The method of claim 5 , wherein the tamper-proof circuit is configured to cause an IHS shutdown in response to tampering with the chip select circuit.

7. The method of claim 1 , further comprising using a security chip of the IHS to apply an override control to the chip select circuit in response to a transition of a Central Processing Unit (CPU) voltage regulator.

8. An Information Handling System (IHS), comprising:

a chip select circuit;

a first flash memory coupled to the chip select circuit;

a second flash memory coupled to the chip select circuit; and

an Embedded Controller (EC) coupled to the chip select circuit, wherein the EC is configured to:

in a default mode of operation, (a) use the chip select circuit to set the second flash memory active and set the first flash memory inactive, and (b) perform a default boot procedure using the second flash memory; and

in an alternate mode of operation, (a) use the chip select circuit to set the second flash memory inactive and set the first flash memory active, and (b) perform an alternate boot procedure using the first flash memory, wherein to use the chip select circuit, the EC is configured to apply a Real-Time Clock (RTC) battery-powered General-Purpose Input/Output (GPIO) control or external latch circuit to the chip select circuit.

9. The IHS of claim 8 , wherein while in the alternate mode of operation, the chip select circuit is further configured to maintain a security chip in reset.

10. The IHS of claim 8 , further comprising a tamper protection circuit coupled to the chip select circuit, wherein the tamper protection circuit is configured to, in response to a power-on event, pass the RTC battery-powered GPIO control to the output of a logic gate until a Central Processing Unit (CPU) voltage regulator is enabled.

11. The IHS of claim 10 , wherein the tamper protection circuit is further configured to isolate the RTC battery-powered GPIO control from an input of the logic gate in response to a CPU voltage regulator transition.

12. The IHS of claim 11 , wherein the EC is further configured to apply an alternate control to the tamper protection circuit via a flip-flop, and wherein an output of the flip-flop is applied to the logic gate.

13. The IHS of claim 12 , wherein the flip-flop is configured to latch the alternate control to an output of the flip-flop in response to a rising edge of the CPU voltage regulator transition.

14. The IHS of claim 8 , further comprising a security chip coupled to the chip select circuit, wherein the security chip outputs an override control configured to disable the RTC battery-powered GPIO control after the default boot procedure.

15. The IHS of claim 8 , further comprising a flip-flop configured to latch the override control to an output of the flip-flop in response to a rising edge of a CPU voltage regulator transition.

16. A hardware memory device having program instructions stored thereon that, upon execution by an Embedded Controller (EC) of an Information Handling System (IHS), cause the IHS to:

apply a Real-Time Clock (RTC) battery-powered General-Purpose Input/Output (GPIO) control to the chip select circuit;

in a default mode of operation, (a) use a chip select circuit to set a second flash memory active and set a first flash memory inactive, and (b) perform a default boot procedure using the second flash memory; and

in a diagnostic mode of operation, (a) use the chip select circuit to set the second flash memory inactive and set the first flash memory active, and (b) perform a diagnostic boot procedure using the first flash memory.

17. The hardware memory device of claim 16 , wherein the program instructions, upon execution by the EC, further cause the IHS to hold a security chip in reset using the RTC battery-powered GPIO control, latching and isolating the control while in the diagnostic mode.

18. The hardware memory device of claim 16 , wherein the program instructions, upon execution by the EC, further cause the IHS to:

isolate the RTC battery-powered GPIO control from the chip select circuit after the default boot procedure; and

at least one of: (a) maintain a value of the RTC battery-powered GPIO control applied to the chip select circuit in response to tampering with the chip select circuit; or (b) initiate an IHS shutdown in response to tampering with the chip select circuit.