Programmable analog and digital input/output for power application

1. A threshold comparator block integrated in a programmable logic device (PLD) comprising:

an interface to a programmable fabric of the PLD via a signal wrapper, wherein the programmable fabric comprises a digital fabric and an analog fabric; and

one or more signal comparators configured to receive two analog input signals from the analog fabric of the programmable fabric and provide a digital output signal indicating a comparison result of the two analog input signals to the digital fabric of the programmable fabric,

wherein the threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programable fabric and the signal wrapper.

2. The threshold comparator block of claim 1 , further comprising a digital input/output (I/O) driver configured to provide the digital output signal to the digital fabric of the programmable fabric.

3. The threshold comparator block of claim 1 , wherein the digital output signal of the one or more signal comparators indicates a current direction between the two analog input signals.

4. The threshold comparator block of claim 1 , further comprising a summation amplifier configured to receive a plurality of analog input signals including a first analog signal and a second analog signal, and a digital gain and provide an analog output signal to the analog fabric of the programmable fabric that corresponds to a difference between the first analog signal and the second analog signal multiplied by the digital gain.

5. The threshold comparator block of claim 4 , wherein the plurality of analog input signals further includes a third analog signal, and the summation amplifier provides the analog output signal that is offset by the third analog signal.

6. The threshold comparator block of claim 4 , further comprising one or more multiplexers coupled to a plurality of resistors, wherein the one or more multiplexers are configured to receive the digital gain and adjust the digital gain by changing a ratio of the plurality of resistors.

7. The threshold comparator block of claim 4 , further comprising an analog output driver that is configured to drive one or more pins of the PLD and provide the analog output signal to the one or more adaptive blocks integrated in the PLD via the one or more pins.

8. The threshold comparator block of claim 1 , further comprising one or more current source blocks configured to provide a general-purpose input/output (GPIO) interface.

9. The threshold comparator block of claim 8 , wherein I/O signals of the GPIO interface is analog, digital, or a combination of analog and digital signals.

10. The threshold comparator block of claim 8 , wherein the GPIO interface is implemented as a universal serial bus (USB) driver.

11. The threshold comparator block of claim 8 , wherein the one or more current source blocks are connected to a respective pad of the USB driver and are switched on or off using the corresponding switches for USB signals.

12. The threshold comparator block of claim 9 , wherein the USB signals are received via the signal wrapper.

13. A programmable logic device (PLD) comprising:

a threshold comparator block;

a programmable fabric comprising a digital fabric and an analog fabric; and

a signal wrapper configured to provide signals between the threshold comparator block and the programmable fabric; and

input/output (I/O) pins configured to interface analog and digital signals between the threshold comparator block and the programmable fabric via the signal wrapper,

wherein the threshold comparator block comprises:

an interface to the programmable fabric of the PLD via the signal wrapper; and

one or more signal comparators configured to receive two analog input signals from the analog fabric of the programmable fabric and provide a digital output signal indicating a comparison result of the two analog input signals to the digital fabric of the programmable fabric,

wherein the threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programable fabric and the signal wrapper.

14. The PLD of claim 13 , wherein the threshold comparator block further comprises a digital I/O driver configured to provide the digital output signal to the digital fabric of the programmable fabric.

15. The PLD of claim 13 , wherein the threshold comparator block further comprises a summation amplifier configured to receive a plurality of analog input signals including a first analog signal and a second analog signal, and a digital gain and provide an analog output signal to the analog fabric of the programmable fabric that corresponds to a difference between the first analog signal and the second analog signal multiplied by the digital gain.

16. The PLD of claim 15 , wherein the plurality of analog input signals further includes a third analog signal, and the summation amplifier provides the analog output signal that is offset by the third analog signal.

17. The PLD of claim 15 , wherein the threshold comparator block further comprises an analog output driver that is configured to drive one or more pins of the PLD and provide the analog output signal to the one or more adaptive blocks integrated in the PLD via the one or more pins.

18. The PLD of claim 13 , wherein the threshold comparator block further comprises one or more current source blocks configured to provide a general-purpose input/output (GPIO) interface.

19. The PLD of claim 18 , wherein I/O signals of the GPIO interface is analog, digital, or a combination of analog and digital signals.

20. The PLD of claim 18 , wherein the GPIO interface is implemented as a universal serial bus (USB) driver.

21. The PLD of claim 20 , wherein the one or more current source blocks are connected to a respective pad of the USB driver and are switched on or off using the corresponding switches for USB signals.

22. The PLD of claim 21 , wherein the USB signals are received via the signal wrapper.