Low cost, hardened single board computer for command and data handling
A radiation hardened single board computer (SBC) includes a processor; synchronous dynamic random-access memory (SDRAM); non-volatile memory; a field programmable gate array (FPGA); and board-level physical layer interfaces.
1. A radiation hardened single board computer (SBC) comprising:
a processor application-specific integrated circuit (ASIC);
synchronous dynamic random-access memory (SDRAM);
non-volatile memory;
a field programmable gate array (FPGA); and
board-level physical layer interfaces configured to connect to an OpenVPX backplane and a SpaceVPX backplane, wherein the board-level physical layer interfaces comprise:
a SpaceWire connection configured to connect with a Space VPX control plane using a first VPX connector and a second VPX connector; and
an Ethernet connection configured to connect with an OpenVPX control plane using the first VPX connector.
2. The SBC of claim 1 , wherein at least one of the processor ASIC and the FPGA comprise an 8-port SpaceWire router.
3. The SBC of claim 1 , wherein the FPGA comprises an Ethernet switch.
4. The SBC of claim 1 , wherein the SBC is configured to interface with one or more sensor boards via the OpenVPX backplane or the SpaceVPX backplane.
5. The SBC of claim 4 , wherein the FPGA is configured to perform automated error detection and correction for errors found in a plurality of SRAM programming memory of FPGAs of the sensor boards due to radiation induced single event effects.
6. The SBC of claim 1 , wherein the FPGA is configured to provide physical layer support for:
high-speed serial interfaces;
Low-Voltage Differential Signaling (LVDS) interfaces;
an Inter-IC (I2C) interface; and
Joint Test Action Group (JTAG) interfaces.
7. The SBC of claim 1 , wherein the FPGA comprises a flash controller and wherein the nonvolatile memory comprises flash memory managed by the flash controller.
8. The SBC of claim 1 , wherein the SDRAM comprises byte-wide power control and wherein the processor ASIC is configured to power cycle a physical location on the SDRAM when a single-event functional interrupt is detected.
9. The SBC of claim 1 , wherein the processor ASIC is configured to employ Reed-Solomon error encoding on the SDRAM.
10. A radiation hardened single board computer (SBC) comprising:
a processor application-specific integrated circuit (ASIC) comprising a first 8-port SpaceWire router;
synchronous dynamic random-access memory (SDRAM) directly connected to the processor ASIC;
a field programmable gate array (FPGAI) connected to the processor ASIC, wherein the FPGA is configured to perform co-processing functions to reduce the load on the processor ASIC and the FPGA comprises a second 8-port SpaceWire router and an Ethernet switch; and
a board-level physical layer interface comprising a first VPX connector and a second VPX connector, wherein the first and second SpaceWire routers are connected to the first VPX connector and the second VPX connector, and wherein the Ethernet switch is connected to the first VPX connector.
11. The SBC of claim 10 , wherein the first and second SpaceWire routers are connected to the first and second VPX connectors using at least one thin pipe.
12. The SBC of claim 10 , wherein the Ethernet switch is connected to the first VPX connector using at least one ultra-thin pipe.
13. The SBC of claim 10 , wherein the SBC is configured to operate in both SpaceVPX and OpenVPX environments.
14. The SBC of claim 10 , wherein the FPGA comprises a flash controller and wherein the nonvolatile memory comprises flash memory managed by the flash controller.
15. The SBC of claim 10 , wherein the SDRAM comprises byte-wide power control and wherein the processor ASIC is configured to power cycle a physical location on the SDRAM when a single-event functional interrupt is detected.
16. The SBC of claim 10 , wherein the processor ASIC is configured to employ Reed-Solomon error encoding on the SDRAM.
17. A radiation hardened single board computer (SBC) comprising:
a processor application-specific integrated circuit (ASIC);
synchronous dynamic random-access memory (SDRAM), wherein the SDRAM comprises byte-wide power control and wherein the processor ASIC is configured to power cycle a physical location on the SDRAM when a single-event functional interrupt is detected;
non-volatile memory;
a field programmable gate array (FPGA) and;
board-level physical layer interfaces configured to connect to an OpenVPX backplane and a SpaceVPX backplane, wherein the board-level physical layer interfaces comprise:
a SpaceWire connection; and
an Ethernet connection.