Storage device and operating method thereof
There are provided a memory controller for controlling a memory device to perform a more stable sensing operation, a storage device including the memory controller, and an operating method of the storage device. A memory controller includes: a processor for transmitting a cache read command to a memory device and then transmitting a status read command to the memory device; and a cache read controller for outputting a data-out command to the memory device according to a sensing section code included in a status read response transmitted by the memory device in response to the status read command.
1. A memory controller comprising:
a processor configured to transmit a cache read command to a memory device and then transmit a status read command to the memory device; and
a cache read controller configured to output a data-out command to the memory device according to a sensing section code included in a status read response transmitted by the memory device in response to the status read command,
wherein the cache read command is a read command for arbitrary Nth and (N+1)th pages included in the memory device, and
wherein the processor determines whether a read operation on the Nth page has been completed from the status read response.
2. The memory controller of claim 1 , wherein the sensing section code is data indicating that the memory device belongs to a sensing section among a plurality of operation sections included in a read operation.
3. The memory controller of claim 1 , wherein the cache read controller includes:
a status read controller configured to output an enable signal, if the sensing section code is in a disabled status; and
a data-out command controller configured to transmit the data-out command to the memory device in response to the enable signal.
4. The memory controller of claim 3 , wherein the status read controller transmits, if the sensing section code is in a set status, the status read command to the memory device.
5. The memory controller of claim 3 , wherein the status read controller transmits, if a predetermined time elapses from a point of time when the cache read command is transmitted, the status read command to the memory device.
6. The memory controller of claim 1 , wherein the processor transmits, when the read operation on the Nth page is not completed, the status read command to the memory device.
7. The memory controller of claim 1 , wherein the status read response is data stored in a status register for storing an operation status of the memory device.
8. A method for operating a memory controller for controlling a memory device, the method comprising:
transmitting, to the memory device, a cache read command for at least two pages included in the memory device;
transmitting, to the memory device, a status read command for requesting data of a status register storing an operation status of the memory device;
determining whether a read operation on a precedent page among the at least two pages has been completed based on the status read response transmitted by the memory device in response to the status read command; and
transmitting a data-out command to the memory device according to a sensing section code included in a status read response transmitted by the memory device in response to the status read command.
9. The method of claim 8 , wherein the transmitting of the data-out command includes:
determining whether the sensing section code included in the status read response is in a disabled status; and
transmitting, if the sensing section code is in the disabled status, the data-out command to the memory device.
10. The method of claim 9 , further comprising re-transmitting, if the sensing section code included in the status read response is in a set status, the status read command to the memory device.
11. The method of claim 8 , further comprising re-transmitting, when the read operation on the precedent page among the at least two pages is not completed, the status read command to the memory device.
12. The method of claim 8 , wherein the sensing section code is data indicating that the memory device belongs to a sensing section among a plurality of operation sections included in a read operation.
13. A storage device comprising:
a memory device configured to perform an operation corresponding to a cache read command for at least two pages; and
a memory controller configured to transmit a data-out command to the memory device, based on a sensing section code included in a status read response transmitted by the memory device in response to a status read command transmitted to the memory device,
wherein the memory device includes a status register for storing data on an operation status of the memory device, and
wherein the data of the status register includes ready information indicating that a read operation of a precedent page among the at least two pages has been completed and the sensing section code.
14. The storage device of claim 13 , wherein the status read response includes data of the status register.
15. The storage device of claim 13 , wherein the sensing section code is data indicating that the memory device belongs to a sensing section for storing data of a memory cell in a page buffer among a plurality of operation sections included in a read operation.
16. The storage device of claim 15 , wherein the memory controller transmits, if the sensing section code is in a disabled status, the data-out command to the memory device.