IP Library Granted Patent US 10,678,730
Granted Patent B2
US 10,678,730 · App. 15/990,772 · Granted Jun 9, 2020

Computing system framework and method for configuration thereof

Inventor: Daniel Davies (Palo Alto, CA)
Assignee: Palo Alto Research Center Incorporated
G06F13/4022G06F13/4265G06F15/17362
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,678,730
App. No.
15/990,772
Granted
Jun 9, 2020
Kind
B2
Abstract

A computing system framework and method for configuration thereof are provided. A plurality of processing modules is accessed. Each processing module includes a plurality of processing nodes and each processing node is associated with an intramodule port and an intermodule port. The processing modules are connected in a ring via intermodule connections between at least a portion of the intermodule ports of the processing modules. A network switch is arranged in a center of the ring of processing modules and connections are formed between the network switch and at least one of the processing modules by connecting every Sth processing module to the network switch, connecting every Sth and Sth−1 processing modules to the network switch, or by connecting every Sth and Sth−r processing modules to the network switch. S is a number of steps between the processing modules.

Claims (37)

1. A computing system framework, comprising:

a plurality of processing modules, each processing module comprising a plurality of processing nodes and each processing node associated with an intramodule port and an intermodule port;

a ring formed of the processing modules via intermodule connections between at least a portion of the intermodule ports of the processing modules;

a network switch arranged in a center of the ring of processing modules;

connections formed between the network switch and at least one of the processing modules, comprising at least one of:

a connection between the network switch and only every Sth processing module, wherein S is a number of steps between the processing modules and is greater than 1;

a connection between the network switch and only every Sth and Sth−1 processing modules, wherein S is greater than 2; and

a connection between the network switch and only every Sth and Sth−r processing modules, wherein r is a different number of steps between the processing modules than the number of steps of S, which is greater than 2.

2. A computing system framework according to claim 1 , wherein the intermodule connection between each pair of the Sth and the Sth−1 processing modules is removed.

3. A computing system framework according to claim 1 , wherein the processing module N and the processing module N+S−1 are connected to the network switch, when every Sth and Sth−1 processing modules are connected to the network switch.

4. A computing system framework according to claim 1 , wherein the processing module N and the processing module N+S−r are connected to the network switch when every Sth and Sth−r processing modules are connected to the network switch, wherein M is a number of the processing modules.

5. A computing system framework according to claim 1 , wherein the ring of processing modules is connected to a further ring of processing modules by linking via a cable one of the intermodule ports on one of the processing modules of the ring with one of the intermodule ports on one of the processing modules of the further ring.

6. A computing system framework according to claim 1 , further comprising:

one or more further network switches to connect at least one of an external device and one or more further rings of processing nodes to the ring of processing nodes.

7. A computing system framework according to claim 1 , wherein data packets are transferred through the intermodule connections from one of the processing nodes of one of the processing modules in the ring to another processing node of another processing module in the ring.

8. A computing system framework according to claim 7 , wherein traffic of the data packet transfer is measured and the intermodule connections are amended based on the traffic.

9. A computing system framework according to claim 1 , wherein at least one of the intermodule ports on one of the processing modules is connected to at least one intermodule port on another processing module using a hybrid system.

10. A method for constructing a computing system framework, comprising:

accessing a plurality of processing modules, each processing module comprising a plurality of processing nodes and each processing node associated with an intramodule port and an intermodule port;

connecting the processing modules in a ring via intermodule connections between at least a portion of the intermodule ports of the processing modules;

arranging a network switch in a center of the ring of processing modules;

forming connections between the network switch and at least one of the processing modules, comprising at least one of:

connecting only every Sth processing module to the network switch, wherein S is a number of steps between the processing modules and is greater than 1;

connecting only every Sth and Sth−1 processing modules to the network switch, wherein S is greater than 2; and

connecting only every Sth and Sth−r processing modules to the network switch, wherein r is a different number of steps between the processing modules than the number of steps of S, which is greater than 2.

11. A method according to claim 10 , wherein the intermodule connection between each pair of the Sth and the Sth−1 processing modules is removed.

12. A method according to claim 10 , wherein the processing module N and the processing module N+S−1 are connected to the network switch, when every Sth and Sth−1 processing modules are connected to the network switch.

13. A method according to claim 10 , wherein the processing module N and the processing module N+S-r are connected to the network switch when every Sth and Sth−r processing modules are connected to the network switch, wherein M is a number of the processing modules.

14. A method according to claim 10 , further comprising:

connecting to the ring of processing modules a further ring of processing modules, wherein each ring of processing nodes comprises a block, by linking via a cable one of the intermodule ports on one of the processing modules of one block with one of the intermodule ports on one of the processing modules of the other block.

15. A method according to claim 10 , further comprising:

connecting to the ring of processing nodes at least one of an external device and one or more further rings of processing nodes via one or more further network switches.

16. A method according to claim 10 , wherein data packets are transferred through the intermodule connections from one of the processing nodes of one of the processing modules in the ring to another processing node of another processing module in the ring.

17. A method according to claim 16 , further comprising:

measuring traffic of the data packet transfer; and

amending the intermodule connections based on the traffic.

18. A method according to claim 10 , wherein at least one of the intermodule ports on one of the processing modules is connected to at least one intermodule port on another processing module using a hybrid system.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2025
From: XEROX CORPORATION
To: GENESEE VALLEY INNOVATIONS, LLC
Reel/Frame 073562/0677 →
SECOND LIEN NOTES PATENT SECURITY AGREEMENT Recorded Jul 2, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 071785/0550 →
FIRST LIEN NOTES PATENT SECURITY AGREEMENT Recorded Apr 11, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 070824/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RF 064760/0389 Recorded Feb 13, 2024
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: XEROX CORPORATION
Reel/Frame 068261/0001 →
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVAL OF US PATENTS 9356603, 10026651, 10626048 AND INCLUSION OF US PATENT 7167871 PREVIOUSLY RECORDED ON REEL 064038 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 28, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064161/0001 →
SECURITY INTEREST Recorded Jun 22, 2023
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 064760/0389 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064038/0001 →
Continuity (4)
Continuation 15645883 · Jul 10, 2017
Continuation 14512341 · Oct 10, 2014
Continuation In Part 14313922 · Jun 24, 2014
Related Publication 20180276162A1 · Sep 27, 2018