Broadband phase locked loop for multi-band millimeter-wave 5G communication
View Patent ↗According to one embodiment, a phase locked loop (PLL) circuit includes a first voltage controlled oscillator (VCO) to generate a first signal having a first frequency and a second VCO to generate a second signal having a second frequency. The PLL circuit includes a multiplexer coupled to the first VCO, the second VCO, and a feedback loop. The PLL circuit includes a control logic to select either the first VCO or the second VCO using the multiplexer to feed back a signal using the feedback loop, and a phase frequency detector coupled to the first VCO, the second VCO, and the feedback loop, where the phase frequency detector is configured to receive a reference signal and the feedback signal to tracking a frequency and a phase of the first or the second generated signal using the reference signal and the feedback signal.
1. A phase locked loop (PLL) circuit, the circuit comprising:
a first voltage controlled oscillator (VCO) to generate a first signal having a first frequency in a first frequency band;
a second VCO to generate a second signal having a second frequency in a second frequency band, wherein the second frequency band is a different frequency band than the first frequency band;
a multiplexer coupled to the first VCO, the second VCO, and a feedback loop;
a control logic to select either the first VCO or the second VCO using the multiplexer to feed back a signal associated with the first VCO or the second VCO using the feedback loop; and
a phase frequency detector coupled to the first VCO, the second VCO, and the feedback loop, wherein the phase frequency detector is configured to receive a reference signal and a feedback signal to track a frequency and a phase of the first or the second generated signal using the reference signal and the feedback signal, wherein the first frequency range is approximately 18.5 GHz to 26.5 GHz and the second frequency range is approximately 31.5 GHz to 41.5 GHz.
2. The PLL circuit of claim 1 , wherein the phase locked loop circuit generates a first local oscillator (LO) signal having the first frequency or a second LO signal having the second frequency, wherein the first frequency and the second frequency are both first harmonics.
3. The PLL circuit of claim 1 , further comprising:
a first current model logic (CML) frequency divider circuit coupled in between the first VCO and the multiplexer; and
a second CML frequency divider circuit coupled in between the second VCO and the multiplexer.
4. The PLL circuit of claim 3 , wherein the first or the second CML frequency divider circuit is a 1/16 frequency divider.
5. The PLL circuit of claim 3 , further comprising:
a first digital frequency divider circuit coupled in between the first CML and the multiplexer; and
a second digital frequency divider circuit coupled in between the second CML and the multiplexer.
6. The PLL circuit of claim 1 , further comprising a low pass filter coupled in between the phase frequency detector and the first and the second VCOs, wherein the low pass filter is a third order low pass filter.
7. The PLL circuit of claim 6 , wherein the third order low pass filter includes a passive resistor-capacitor network having three separate resonant frequencies.
8. The PLL circuit of claim 1 , wherein the control logic further disables one of the first VCO or the second VCO that is not selected.
9. A phase locked loop (PLL) circuit, the circuit comprising:
a first voltage controlled oscillator (VCO) to generate a first signal having a first frequency in a first frequency band;
a second VCO to generate a second signal having a second frequency in a second frequency band, wherein the second frequency band is a different frequency band than the first frequency band;
a multiplexer coupled to the first VCO, the second VCO, and a feedback loop;
a control logic to select either the first VCO or the second VCO using the multiplexer to feed back a signal associated with the first VCO or the second VCO using the feedback loop;
a phase frequency detector coupled to the first VCO, the second VCO, and the feedback loop, wherein the phase frequency detector is configured to receive a reference signal and a feedback signal to track a frequency and a phase of the first or the second generated signal using the reference signal and the feedback signal;
a first current model logic (CML) frequency divider circuit coupled in between the first VCO and the multiplexer;
a second CML frequency divider circuit coupled in between the second VCO and the multiplexer;
a first digital frequency divider circuit coupled in between the first CML and the multiplexer; and
a second digital frequency divider circuit coupled in between the second CML and the multiplexer, wherein the first or the second digital frequency divider circuit is selectable from 1/16 to 1/63 frequency divisions.
10. A radio frequency (RF) frontend circuit comprising a phase locked loop circuit to generate a local oscillator (LO) signal, the phase locked loop circuit comprising:
a first voltage controlled oscillator (VCO) to generate a first signal having a first frequency in a first frequency band;
a second VCO to generate a second signal having a second frequency in a second frequency band, wherein the second frequency band is a different frequency band than the first frequency band;
a multiplexer coupled to the first VCO, the second VCO, and a feedback loop;
a control logic to select either the first VCO or the second VCO using the multiplexer to feed back a signal associated with the first VCO or the second VCO using the feedback loop; and
a phase frequency detector coupled to the first VCO, the second VCO, and the feedback loop, wherein the phase frequency detector is configured to receive a reference signal and a feedback signal to track a frequency and a phase of the first or the second generated signal using the reference signal and the feedback signal, wherein the first frequency range is approximately 18.5 GHz to 26.5 GHz and the second frequency range is approximately 31.5 GHz to 41.5 GHz.
11. The RF frontend circuit of claim 10 , wherein the phase locked loop circuit generates a first LO having the first frequency or a second LO having the second frequency, wherein the first frequency and the second frequency are both first harmonics.
12. The RF frontend circuit of claim 10 , wherein the phase locked loop circuit further comprises:
a first current model logic (CML) frequency divider circuit coupled in between the first VCO and the multiplexer; and
a second CML frequency divider circuit coupled in between the second VCO and the multiplexer.
13. The RF frontend circuit of claim 12 , wherein the first or the second CML frequency divider circuit is a 1/16 frequency divider.
14. The RF frontend circuit of claim 12 , wherein the phase locked loop circuit further comprises:
a first digital frequency divider circuit coupled in between the first CML and the multiplexer; and
a second digital frequency divider circuit coupled in between the second CML and the multiplexer.
15. The RF frontend circuit of claim 10 , wherein the phase locked loop circuit further comprises a low pass filter coupled in between the phase frequency detector and the first and the second VCOs, wherein the low pass filter is a third order low pass filter.
16. The RF frontend circuit of claim 15 , wherein the third order low pass filter includes a passive resistor-capacitor network having three separate resonant frequencies.
17. The RF frontend circuit of claim 10 , wherein the control logic further disables one of the first VCO or the second VCO that is not selected.
18. A radio frequency (RF) frontend circuit comprising a phase locked loop circuit to generate a local oscillator (LO) signal, the phase locked loop circuit comprising:
a first voltage controlled oscillator (VCO) to generate a first signal having a first frequency in a first frequency band;
a second VCO to generate a second signal having a second frequency in a second frequency band, wherein the second frequency band is a different frequency band than the first frequency band;
a multiplexer coupled to the first VCO, the second VCO, and a feedback loop;
a control logic to select either the first VCO or the second VCO using the multiplexer to feed back a signal associated with the first VCO or the second VCO using the feedback loop;
a phase frequency detector coupled to the first VCO, the second VCO, and the feedback loop, wherein the phase frequency detector is configured to receive a reference signal and a feedback signal to track a frequency and a phase of the first or the second generated signal using the reference signal and the feedback signal;
a first current model logic (CML) frequency divider circuit coupled between the first VCO and the multiplexer;
a second CML frequency divider circuit coupled in between the second VCO and the multiplexer;
a first digital frequency divider circuit coupled in between the first CML and the multiplexer; and
a second digital frequency divider circuit coupled in between the second CML and the multiplexer, wherein the first or the second digital frequency divider circuit is selectable from 1/16 to 1/63 frequency divisions.