IP Library Granted Patent US 10,467,184
Granted Patent B2
US 10,467,184 · App. 15/994,451 · Granted Nov 5, 2019

Parallel processing apparatus, parallel computing method, and recording medium storing parallel computing program

Inventors: Jun Fujisaki (Kawasaki, JP); Ryoji Tandokoro (Fujisawa, JP); Akira Hosoi (Atsugi, JP); Hideyuki Shitara (Toda, JP)
Assignee: FUJITSU LIMITED
G06F15/803G06F15/82G06F17/12
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Quick Facts
Patent No.
US 10,467,184
App. No.
15/994,451
Granted
Nov 5, 2019
Kind
B2
Abstract

A parallel processing apparatus includes: processors; and a network switch, wherein a first processor: generates divided matrix data by dividing the matrix data in such a manner that an overlapping portion is present with each other; transmits the divided matrix data to a second processor; generates first evaluation-value matrix data from the divided matrix data; transmits, to the second processor, first elements in a first overlapping portion of the first evaluation-value matrix data; receives, from the second processor, second elements of a second overlapping portion of second evaluation-value matrix data; calculates first added evaluation data by adding the second elements to the first elements; transmits the first added evaluation data to the second processor; receives, from the second processor, second added evaluation data; and calculates a first C point or a first F point based on the first evaluation-value matrix data which is updated using the second added evaluation data.

Claims (50)

1. A parallel processing apparatus comprising:

a plurality of processors; and

a network switch that couples the plurality of processors to each other,

wherein a first processor among the plurality of processors:

generates divided matrix data, when processing matrix data using a parallel processing based on an algebraic multigrid method and determining a C point or an F point, by dividing the matrix data in such a manner that an overlapping portion is present with each other;

transmits the divided matrix data to a second processor which is different from the first processor and is included in the plurality of processors;

generates first evaluation-value matrix data from the divided matrix data;

transmits, to the second processor, first elements in a first overlapping portion of the first evaluation-value matrix data;

receives, from the second processor, second elements of a second overlapping portion of second evaluation-value matrix data which is generated by the second processor;

calculates first added evaluation data by adding the second elements to the first elements;

transmits the first added evaluation data to the second processor;

receives, from the second processor, second added evaluation data which is calculated by the second processor; and

calculates a first C point or a first F point based on the first evaluation-value matrix data which is updated by inputting the second added evaluation data to the first evaluation-value matrix data.

2. The parallel processing apparatus according to claim 1 ,

wherein the first processor:

transmits information on the first C point or the first F point to the second processor; and

receives, from the second processor, information on a second C point or a second F point which is calculated by the second processor.

3. The parallel processing apparatus according to claim 2 ,

wherein the first processor:

updates the first C point or the first F point of the first element in the first overlapping portion based on the information on the second C point or the second F point.

4. A parallel computing method comprising:

generating, by a first processor of a plurality of processors which are coupled by a network switch with each other, divided matrix data, when processing matrix data using a parallel processing based on an algebraic multigrid method and determining a C point or an F point, by dividing the matrix data in such a manner that an overlapping portion is present with each other;

transmitting the divided matrix data to a second processor which is different from the first processor and is included in the plurality of processors;

generating first evaluation-value matrix data from the divided matrix data;

transmitting, to the second processor, first elements in a first overlapping portion of the first evaluation-value matrix data;

receiving, from the second processor, second elements of a second overlapping portion of second evaluation-value matrix data which is generated by the second processor;

calculating first added evaluation data by adding the second elements to the first elements;

transmitting the first added evaluation data to the second processor;

receiving, from the second processor, second added evaluation data which is calculated by the second processor; and

calculating a first C point or a first F point based on the first evaluation-value matrix data which is updated by inputting the second added evaluation data to the first evaluation-value matrix data.

5. The parallel processing apparatus according to claim 4 , further comprising:

transmitting, by the first processor, information on the first C point or the first F point to the second processor; and

receiving, from the second processor, information on a second C point or a second F point which is calculated by the second processor.

6. The parallel processing apparatus according to claim 5 , further comprising:

updating the first C point or the first F point of the first element in the first overlapping portion based on the information on the second C point or the second F point.

7. A non-transitory computer-readable recording medium storing a parallel computing program which causes a computer to preform a process, the process comprising:

generating divided matrix data, when processing matrix data using a parallel processing based on an algebraic multigrid method and determining a C point or an F point, by dividing the matrix data in such a manner that an overlapping portion is present with each other;

transmitting the divided matrix data from a first processor to a second processor which is different from the first processor and is included in the plurality of processors;

generating first evaluation-value matrix data from the divided matrix data;

transmitting, to the second processor, first elements in a first overlapping portion of the first evaluation-value matrix data;

receiving, from the second processor, second elements of a second overlapping portion of second evaluation-value matrix data which is generated by the second processor;

calculating first added evaluation data by adding the second elements to the first elements;

transmitting the first added evaluation data to the second processor;

receiving, from the second processor, second added evaluation data which is calculated by the second processor; and

calculating a first C point or a first F point based on the first evaluation-value matrix data which is updated by inputting the second added evaluation data to the first evaluation-value matrix data.

8. The parallel processing apparatus according to claim 7 , further comprising:

transmitting, by the first processor, information on the first C point or the first F point to the second processor; and

receiving, from the second processor, information on a second C point or a second F point which is calculated by the second processor.

9. The parallel processing apparatus according to claim 8 , further comprising:

updating the first C point or the first F point of the first element in the first overlapping portion based on the information on the second C point or the second F point.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL COVER SHEET BY REMOVING PATENT NUMBER 10586039 PREVIOUSLY RECORDED ON REEL 69272 FRAME 546. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 1, 2025
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 070764/0091 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2024
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 069272/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2018
From: FUJISAKI, JUN; TANDOKORO, RYOJI; HOSOI, AKIRA; SHITARA, HIDEYUKI
To: FUJITSU LIMITED
Reel/Frame 045958/0608 →
Priority Claims (1)
JP 2017-110981 · Jun 5, 2017 · national
Continuity (1)
Related Publication 20180349316A1 · Dec 6, 2018