IP Library Granted Patent US 10,789,200
Granted Patent B2
US 10,789,200 · App. 15/995,708 · Granted Sep 29, 2020

Server message block remote direct memory access persistent memory dialect

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Quick Facts
Patent No.
US 10,789,200
App. No.
15/995,708
Granted
Sep 29, 2020
Kind
B2
Abstract

A multiple processor system comprising a first processor configured to utilize an inter-processor messaging protocol and a second processor configured to utilize the inter-processor messaging protocol is disclosed. The system includes a non-volatile memory device coupled to the first processor, wherein the second processor is configured to access the non-volatile memory device by utilizing the inter-processor messaging protocol.

Claims (21)

1. A multiple processor system comprising:

a first processor configured to utilize a server message block protocol;

a second processor configured to utilize the server message block protocol;

a non-volatile memory device coupled to the first processor;

wherein the second processor is configured to push and pull data from the non-volatile memory device by utilizing remote direct memory access queues in conjunction with non-volatile memory queues and an entry in a non-volatile dual in-line memory (NVDIMM) firmware interface table (NFIT), wherein the non-volatile memory queues are integrated with a network interface controller receive list and the entry is an NFIT namespace entry marked as remote access capable during pre-boot;

wherein the second processor utilizes remote direct memory access queues to perform server message block protocol metadata command processing;

wherein the remote direct memory access queues include an event queue and a queue pair; and

wherein the second processor utilizes reconnectable binary language objects to provide naming permissions.

2. The multiple processor system of claim 1 , wherein a label is provided for the NFIT namespace entry during pre-boot.

3. The multiple processor system of claim 1 , wherein a label is provided with a sublabel for the NFIT namespace during pre-boot.

4. The multiple processor system of claim 1 , wherein a label is provided with a sublabel and a remote PMEM enable for the NFIT namespace during pre-boot.

5. A method for controlling a multiple processor system comprising:

configuring a first processor to utilize a server message block protocol;

configuring a second processor to utilize the server message block protocol;

wherein the second processor is configured to push and pull data from a non-volatile memory device coupled to the first processor by utilizing remote direct memory access queues in conjunction with non-volatile memory queues and an entry in a non-volatile dual in-line memory (NVDIMM) firmware interface table (NFIT), wherein the non-volatile memory queues are integrated with a network interface controller receive list and the entry is an NFIT namespace entry marked as remote access capable during pre-boot;

wherein the second processor utilizes the remote direct memory access queues to perform server message block protocol metadata command processing;

wherein the remote direct memory access queues include an event queue and a queue pair; and

wherein the second processor utilizes reconnectable binary language objects to provide naming permissions.

6. The method of claim 5 wherein a label is provided for the NFIT namespace entry during pre-boot.

7. The method of claim 5 wherein a label is provided with a sublabel for the NFIT namespace during pre-boot.

8. The method of claim 5 wherein a label is provided with a sublabel and a remote PMEM enable for the NFIT namespace during pre-boot.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (047648/0422) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060160/0862 →
RELEASE OF SECURITY INTEREST AT REEL 047648 FRAME 0346 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058298/0510 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Oct 12, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 047648/0346 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Oct 12, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 047648/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2018
From: VIDYADHARA, SUMANTH; SURYANARAYANA, SHEKAR BABU
To: DELL PRODUCTS L.P.
Reel/Frame 046287/0305 →