IP Library Granted Patent US 10,332,732
Granted Patent B1
US 10,332,732 · App. 15/995,946 · Granted Jun 25, 2019

Image intensifier with stray particle shield

Inventors: Arlynn W. Smith (Blue Ridge, VA); Dan Chilcott (Buchanan, VA)
Assignee: Eagle Technology, LLC
H01J43/02H01J1/34H01J31/506H01J40/16H01J43/08H01J43/12
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Quick Facts
Patent No.
US 10,332,732
App. No.
15/995,946
Granted
Jun 25, 2019
Kind
B1
Abstract

A light intensifier includes a semiconductor structure to multiply electrons and block stray particles (e.g., photons and/or ions). The semiconductor structure includes an electron multiplier region that is doped to generate a plurality of electrons for each electron that impinges a reception surface of the semiconductor structure, blocking regions that are doped to direct the plurality of electrons towards emissions areas of an emission surface of the semiconductor structure, and shielding regions that are doped to absorb stray particles that impinge the emission surface of the semiconductor structure.

Claims (65)

1. An apparatus, comprising:

a semiconductor structure that includes,

an electron multiplier region that is doped to generate a plurality of electrons for each electron that impinges a reception surface of the semiconductor structure;

a blocking region that is doped to repel the plurality of electrons towards an emission area of an emission surface of the semiconductor structure; and

a shielding region that is doped to absorb stray particles that impinge the emission surface of the semiconductor structure, wherein the stray particles include one or more of stray photons and stray ions.

2. The apparatus of claim 1 , wherein:

the shielding region is doped to convert the stray particles to respective pairs of stray electrons and stray holes, and to recombine the stray electrons with the stray holes.

3. The apparatus of claim 1 , wherein:

the blocking region and the electron multiplier region are doped with a P-type dopant; and

the shielding region is doped with an N-type dopant.

4. The apparatus of claim 1 , wherein:

the blocking region extends from the emission surface of the semiconductor structure towards the reception surface of the semiconductor structure; and

the shielding region is within the blocking region.

5. The apparatus of claim 1 , wherein:

the blocking region includes a plurality of blocking regions, each doped to repel the plurality of electrons towards respective adjacent emissions areas of the emission surface of the semiconductor structure; and

the shielding region includes a plurality of shielding regions, each doped to absorb stray particles that impinge respective regions of the emission surface of the semiconductor structure.

6. The apparatus of claim 5 , wherein:

the plurality of blocking regions include multiple rows of blocking channels that extend from the emission surface of the semiconductor structure toward the reception surface of the semiconductor structure; and

the plurality of shielding regions include multiple shielding channels, each positioned within a respective one of the blocking channels.

7. The apparatus of claim 6 , wherein:

the multiple rows of blocking channels includes a first and second rows of blocking channels; and

the first row of blocking channels is perpendicular to the second row of blocking channels.

8. The apparatus of claim 1 , wherein:

the semiconductor substrate is configured as an array of cells that are configured similar to one another; and

a first one of the cells includes the shielding region, the blocking region within the shielding region, and the emission area within the blocking region.

9. The apparatus of claim 1 , wherein:

the blocking region includes a 2-dimensional array of blocking areas on the emission surface of the semiconductor structure;

the emission area includes a 2-dimensional array of emission areas, each within a respective one of the blocking areas; and

the shielding region encompasses a remaining portion of the emission surface of the semiconductor structure.

10. The apparatus of claim 1 , further including:

a photo-cathode to convert protons to electrons and to direct the electrons toward the reception surface of the semiconductor structure; and

an anode to receive the plurality of electrons from the semiconductor structure.

11. A method, comprising:

generating a plurality of electrons for each electron that impinges a reception surface of a semiconductor structure, within an electron multiplier region of a semiconductor structure;

repelling the plurality of electrons from blocking regions of the semiconductor structure that are doped to repel electrons, towards emissions areas of an emission surface of the semiconductor structure; and

absorbing stray particles that impinge the emission surface of the semiconductor structure within shielding regions of the semiconductor structure that are doped to absorb photons, wherein the stray particles include one or more of stray photons and stray ions.

12. The method of claim 11 , wherein the absorbing includes:

converting the stray particles to respective pairs of stray electrons and stray holes within the shielding regions; and

recombining the stray electrons with the stray holes within the shielding regions.

13. The method of claim 11 , wherein:

the blocking region and the electron multiplier region are doped with a P-type dopant; and

the shielding region is doped with an N-type dopant.

14. The method of claim 11 , wherein:

the blocking region extends from the emission surface of the semiconductor structure towards the reception surface of the semiconductor structure; and

the shielding region is within the blocking region.

15. The method of claim 11 , wherein:

the blocking region includes a plurality of blocking regions, each doped to repel the plurality of electrons towards respective adjacent emissions areas of the emission surface of the semiconductor structure; and

the shielding region includes a plurality of shielding regions, each doped to absorb stray particles that impinge respective regions of the emission surface of the semiconductor structure.

16. The method of claim 15 , wherein:

the plurality of blocking regions include multiple rows of blocking channels that extend from the emission surface of the semiconductor structure toward the reception surface of the semiconductor structure; and

the plurality of shielding regions include multiple shielding channels, each positioned within a respective one of the blocking channels.

17. The method of claim 16 , wherein:

the multiple rows of blocking channels includes a first and second rows of blocking channels; and

the first row of blocking channels is perpendicular to the second row of blocking channels.

18. The method of claim 11 , wherein:

the semiconductor substrate is configured as an array of similarly configured cells; and

a first one of the cells includes the shielding region, the blocking region within the shielding region, and the emission area within the blocking region.

19. The method of claim 11 , wherein:

the blocking region includes a 2 -dimensional array of blocking areas on the emission surface of the semiconductor structure;

the emission area includes a 2 -dimensional array of emission areas, each within a respective one of the blocking areas; and

the shielding region encompasses a remaining portion of the emission surface of the semiconductor structure.

20. The method of claim 11 , further including:

converting protons to electrons with a photo-cathode;

directing the electrons from the photo-cathode toward the reception surface of the semiconductor structure; and

receiving the plurality of electrons from the semiconductor structure at an anode.

Assignments (6)
SECURITY INTEREST Recorded Feb 21, 2024
From: ELBIT SYSTEMS OF AMERICA, LLC; SPARTON CORPORATION; SPARTON DELEON SPRINGS, LLC; LOGOS TECHNOLOGIES LLC; ELBITAMERICA, INC.; KMC SYSTEMS, INC.
To: CAPITAL ONE, NATIONAL ASSOCIATION, AS AGENT
Reel/Frame 066642/0935 →
RELEASE OF SECURITY INTEREST Recorded Feb 21, 2024
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: ELBIT SYSTEMS OF AMERICA, LLC
Reel/Frame 066644/0612 →
CHANGE OF NAME Recorded Sep 17, 2019
From: HARRIS CORPORATION
To: L3HARRIS TECHNOLOGIES, INC.
Reel/Frame 050409/0288 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2019
From: L3HARRIS TECHNOLOGIES, INC.; EAGLE TECHNOLOGY, LLC
To: ELBIT SYSTEMS OF AMERICA, LLC
Reel/Frame 050375/0008 →
SECURITY INTEREST Recorded Sep 13, 2019
From: ELBIT SYSTEMS OF AMERICA, LLC
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 050375/0425 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2018
From: SMITH, ARLYNN W.; CHILCOTT, DAN
To: EAGLE TECHNOLOGY, LLC
Reel/Frame 045965/0748 →