System and method for low-power digital signal processing

1. A low-power digital processing circuit comprising:

at least one module operable to, at least:

receive a first signal, where a level of the first signal is represented by a first type of digital representation;

generate a second signal by, at least in part, representing the level of the received first signal by a second type of digital representation different from the first type of digital representation;

generate a third signal by at least in part filtering the second signal; and

generate a fourth signal by, at least in part, representing a level of the third signal by the first type of digital representation,

wherein the at least one module is operable to represent the level of the received first signal by the second type of digital representation by, at least in part, operating to add a DC offset to the level of the first signal represented by the first type of digital representation.

2. The low-power digital processing circuit of claim 1 , wherein the digital processing circuit comprises a digital receiver.

3. A low-power digital processing circuit comprising:

at least one module operable to, at least:

receive a first signal, where a level of the first signal is represented by a first type of digital representation;

generate a second signal by, at least in part, representing the level of the received first signal by a second type of digital representation different from the first type of digital representation;

generate a third signal by at least in part filtering the second signal; and

generate a fourth signal by, at least in part, representing a level of the third signal by the first type of digital representation,

wherein the at least one module is operable to represent the level of the received first signal by the second type of digital representation by, at least in part, operating to multiply the level of the first signal represented by the first type of digital representation by a gain value.

4. A low-power digital processing circuit comprising:

at least one module operable to, at least:

receive a first signal, where a level of the first signal is represented by a first type of digital representation;

generate a second signal by, at least in part, representing the level of the received first signal by a second type of digital representation different from the first type of digital representation;

generate a third signal by at least in part filtering the second signal; and

generate a fourth signal by, at least in part, representing a level of the third signal by the first type of digital representation,

wherein the at least one module is operable to generate a sub-band signal by, at least in part, operating to perform a Fast Fourier Transform (FFT) operation on the fourth signal.

5. A low-power digital processing circuit comprising:

at least one module operable to, at least:

receive a first signal, where a level of the first signal is represented by a first type of digital representation;

generate a second signal by, at least in part, representing the level of the received first signal by a second type of digital representation different from the first type of digital representation;

generate a third signal by at least in part filtering the second signal; and

generate a fourth signal by, at least in part, representing a level of the third signal by the first type of digital representation;

generate a fifth signal by at least in part representing the level of the received first signal by a third type of digital representation different from the first type of digital representation;

generate a sixth signal by, at least in part, filtering the fifth signal; and

generate a seventh signal by, at least in part, representing the level of the sixth signal by the first type of digital representation.

6. The low-power digital receiver of claim 5 , wherein the at least one module is operable to generate a second sub-band signal by, at least in part, operating to perform a Fast Fourier Transform (FFT) operation on the seventh signal.

7. The low-power digital receiver of claim 5 , wherein the at least one module is operable to generate the second signal and to generate the fifth signal simultaneously.

8. A low-power digital processing circuit comprising:

at least one module operable to, at least:

receive a first signal, where a level of the first signal is represented by a first type of digital representation;

generate a second signal by at least in part first adjusting the first type of digital representation of the level of the first signal to a second type of digital representation, wherein said first adjusting comprises adding a first DC offset;

generate a third signal by at least in part filtering the second signal; and

generate a fourth signal by, at least in part, representing a level of the third signal by the first type of digital representation.

9. The low-power digital processing circuit of claim 8 , wherein the second type of digital representation is the first type of digital representation adjusted by the first DC offset.

10. The low-power digital processing circuit of claim 8 , wherein the at least one module operates to filter the second signal by, at least in part, operating to:

first multiply the second signal by a first magnitude of a first tap coefficient to generate a first product signal; and

after the first multiplying, incorporate a sign of the first tap coefficient into the first product signal to generate a first signed product signal.

11. The low-power digital processing circuit of claim 10 , wherein the at least one module operates to filter the second signal by, at least in part, operating to:

time-shift the second signal;

second multiply the time-shifted second signal by a second magnitude of a second tap coefficient to generate a second product signal;

after the second multiplying, incorporate a sign of the second tap coefficient into the second product signal to generate a second signed product signal; and

add the second signed product signal to the first signed product signal.

12. The low-power digital processing circuit of claim 8 , wherein the first DC offset is large enough to ensure that all levels of the second type of digital representation of the level of the first signal are non-negative.

13. A low-power digital processing circuit comprising:

at least one module operable to, at least:

receive a first signal, where a level of the first signal is represented by a first type of digital representation;

generate a second signal by, at least in part, representing the level of the received first signal by a second type of digital representation different from the first type of digital representation;

generate a third signal by, at least in part, performing a digital signal processing function on the second signal; and

generate a fourth signal by, at least in part, representing a level of the third signal by the first type of digital representation,

wherein the at least one module is operable to represent the level of the received first signal by the second type of digital representation by, at least in part, operating to:

add a DC offset to the level of the first signal represented by the first type of digital representation; and/or

multiply the level of the first signal represented by the first type of digital representation by a gain value.

14. A low-power digital processing circuit comprising:

at least one module operable to, at least:

receive a first signal, where a level of the first signal is represented by a first type of digital representation;

generate a second signal by, at least in part, representing the level of the received first signal by a second type of digital representation different from the first type of digital representation;

generate a third signal by, at least in part, performing a digital signal processing function on the second signal; and

generate a fourth signal by, at least in part, representing a level of the third signal by the first type of digital representation,

wherein the at least one module is operable to generate a sub-band signal by, at least in part, operating to perform a Fast Fourier Transform (FFT) operation on the fourth signal.

15. A low-power digital processing circuit comprising:

at least one module operable to, at least:

receive a first signal, where a level of the first signal is represented by a first type of digital representation;

generate a second signal by, at least in part, representing the level of the received first signal by a second type of digital representation different from the first type of digital representation;

generate a third signal by, at least in part, performing a digital signal processing function on the second signal; and

generate a fourth signal by, at least in part, representing a level of the third signal by the first type of digital representation,

wherein the at least one module is operable to perform the digital signal processing function on the second signal by, at least in part, operating to:

first multiply the second signal by a first magnitude of a first tap coefficient to generate a first product signal; and

after the first multiplying, incorporate a sign of the first tap coefficient into the first product signal to generate a first signed product signal.

16. A low-power digital processing circuit comprising:

at least one module operable to, at least:

receive a first signal, where a level of the first signal is represented by a first type of digital representation;

generate a second signal by, at least in part, representing the level of the received first signal by a second type of digital representation different from the first type of digital representation;

generate a third signal by, at least in part, performing a digital signal processing function on the second signal;

generate a fourth signal by, at least in part, representing a level of the third signal by the first type of digital representation;

generate a fifth signal by, at least in part, representing the level of the received first signal by a third type of digital representation different from the first type of digital representation;

generate a sixth signal by, at least in part, performing a digital signal processing function on the fifth signal; and

generate a seventh signal by, at least in part, representing the level of the sixth signal by the first type of digital representation.

17. The low-power digital receiver of claim 16 , wherein the third digital representation is different from the second digital representation.

18. The low-power digital receiver of claim 16 , wherein the at least one module is operable to generate a second sub-band signal by, at least in part, operating to perform a Fast Fourier Transform (FFT) operation on the seventh signal.