Multiple laser system packaging
A photonic chip comprising tunable lasers, emitters and other optical components such as waveguides, wavelength band combiners and wavelength lockers, is packaged with one or more complementary metal-oxide semiconductor chips in different ways. The complementary metal-oxide semiconductor chips are arranged on the sides or the bottom of the photonic chip. Through-Si-vias or wire bonding provides electrical contact between the photonic chip and the complementary metal-oxide semiconductor chips.
1 . A structure comprising:
a photonic chip comprising a plurality of lasers on at least two of four lateral regions of a top surface of the photonic chip, a plurality of emitters in a central region of the top surface, and a plurality of waveguides on the top surface, the plurality of waveguides connecting the plurality of lasers to the plurality of emitters;
at least two complementary metal-oxide semiconductor (CMOS) chips, each CMOS chip arranged on a different side of the photonic chip; and
wire bonds connecting the at least two CMOS chips to the photonic chip.
2 . The structure of claim 1 , wherein the at least two CMOS chips comprise four CMOS chips.
3 . The structure of claim 2 , wherein the four CMOS chips comprise one CMOS chip per side of the photonic chip.
4 . The structure of claim 1 , wherein each of the plurality of lasers is tunable.
5 . The structure of claim 4 , wherein each of the plurality of lasers comprise a laser array.
6 . The structure of claim 5 , wherein each laser array comprises at least five discrete lasers.
7 . The structure of claim 1 , wherein the plurality of lasers comprises eight lasers.
8 . The structure of claim 7 , wherein the eight lasers are positioned on the photonic chip as two lasers per lateral side.
9 . A structure comprising:
a photonic silicon (Si) chip comprising a plurality of lasers on at least two of four lateral regions of a top surface of the photonic Si chip, a plurality of emitters in a central region of the top surface, and a plurality of waveguides on the top surface, the plurality of waveguides connecting the plurality of lasers to the plurality of emitters;
a complementary metal-oxide semiconductor (CMOS) chip on a bottom surface of the photonic Si chip; and
through-Si-vias connecting the CMOS chip to the photonic Si chip.
10 . A method comprising:
providing a photonic chip;
fabricating a plurality of lasers on at least two of four lateral regions of a top surface of the photonic chip, a plurality of emitters in a central region of the top surface, and a plurality of waveguides on the top surface, the plurality of waveguides connecting the plurality of lasers to the plurality of emitters;
providing at least two complementary metal-oxide semiconductor (CMOS) chips;
arranging each CMOS chip on a different side of the photonic chip; and
connecting by wire bonds the at least two CMOS chips to the photonic chip.
11 . The method of claim 10 , wherein the at least two CMOS chips comprise four CMOS chips.
12 . The method of claim 11 , wherein the four CMOS chips comprise one CMOS chip per side of the photonic chip.
13 . The method of claim 10 , wherein each of the plurality of lasers is tunable.
14 . The method of claim 13 , wherein each of the plurality of lasers comprise a laser array.
15 . The method of claim 14 , wherein each laser array comprises at least five discrete lasers.
16 . The method of claim 10 , wherein the plurality of lasers comprises eight lasers.
17 . The method of claim 16 , wherein the eight lasers are positioned on the photonic chip as two lasers per lateral side.
18 . A method comprising:
providing a photonic Si chip;
fabricating a plurality of lasers on at least two of four lateral regions of a top surface of the photonic Si chip, a plurality of emitters in a central region of the top surface, and a plurality of waveguides on the top surface, the plurality of waveguides connecting the plurality of lasers to the plurality of emitters;
fabricating through-Si-vias in the photonic Si chip;
providing a complementary metal-oxide semiconductor (CMOS) chip;
bonding the CMOS chip on a bottom surface of the photonic Si chip; and
connecting the photonic Si chip to the CMOS chip through an electrical conductor in the through-Si-vias.