Anti-Hebbian and Hebbian (AHAH) computing
Methods, systems and devices for unsupervised learning utilizing at least one kT-RAM. An evaluation can be performed over a group of N AHaH nodes on a spike pattern using a read instruction (FF), and then an increment high (RH) instruction can be applied to the most positive AHaH node among the N AHaH nodes if an ID associated with the most positive AHaH node is not contained in a set, followed by adding a node ID to the set. In addition, an increment low (RL) instruction can be applied to all AHaH nodes that evaluated positive but were not the most positive, contingent on the most-positive AHaH node's ID not being contained in the set. In addition, node ID's can be removed from the set if the set size is equal to the N number of AHaH nodes.
1. A method for unsupervised learning utilizing kT-RAM (Thermodynamic-Random Access Memory), said method comprising:
performing an evaluation over a plurality of N AHaH (Anti-Hebbian and Hebbian) nodes on a spike pattern using a read instruction (FF), wherein each AHaH node among the plurality of N AHaH nodes includes a different pair of synapses comprising at least one memristor;
applying an increment high (RH) feedback instruction to a most positive AHaH node among said N AHaH nodes if an identifier (ID) associated with said most positive AHaH node is not contained in a set, followed by adding a node ID to said set; and
clearing a buffer when a pre-specified amount of evaluation cycles has passed, wherein the buffer allows each AHaH node about the plurality of N AHaH nodes to receive a same amount of Hebbian learning, which facilitates prevention of a single AHaH node among the plurality of N AHaH nodes from capturing a whole phase space, thereby resulting in a partition of phase space across the plurality of N AHaH nodes.
2. The method of claim 1 further comprising applying an increment low (RL) instruction to all AHaH nodes among said plurality of N AHaH nodes that evaluated positive but were not the most positive, contingent on the most-positive AHaH node's ID not being contained in said set.
3. The method of claim 1 further comprising removing all node ID's from said set if a size of the set is equal to said N number of AHaH nodes.
4. The method of claim 1 further comprising removing all node ID's from said set if a total number of said evaluations exceeds a threshold.
5. The method of claim 1 wherein said kT-RAM comprises a neuromorphic processor that implements AHaH computing.
6. An apparatus for unsupervised learning utilizing kT-RAM (Thermodynamic-Random Access Memory), said apparatus comprising:
a plurality of N AHaH (Anti-Hebbian and Hebbian) nodes, wherein an evaluation is performed over said plurality of N AHaH nodes on a spike pattern using a read instruction), wherein each AHaH node among the plurality of N AHaH nodes includes a different pair of synapses comprising at least one memristor;
an increment high (RH) feedback instruction applied to a most positive AHaH node among said N AHaH nodes if an identifier (ID) associated with said most positive AHaH node is not contained in a set, followed by adding a node ID to said set, thereby providing computer memory and processing for a computing system;
a buffer that is cleared when a pre-specified amount of evaluation cycles has passed, wherein the buffer allows each AHaH node about the plurality of N AHaH nodes to receive a same amount of Hebbian learning, which facilitates prevention of a single AHaH node among the plurality of N AHaH nodes from capturing a whole phase space, thereby resulting in a partition of phase space across the plurality of N AHaH nodes.
7. The apparatus of claim 6 wherein an increment low (RL) instruction is applied to all AHaH nodes among said plurality of N AHaH nodes that evaluated positive but were not the most positive, contingent on the most-positive AHaH node's ID not being contained in said set.
8. The apparatus of claim 6 further wherein all node ID's are removed from said set if a size of the set is equal to said N number of AHaH nodes or said all node ID's are removed from said set if a total number of said evaluations exceeds a threshold.
9. The apparatus of claim 6 wherein said kT-RAM comprises emulated kT-RAM emulated via digital circuitry and a processor.
10. The apparatus of claim 9 wherein said processor comprises at least one of: a central processing unit (CPU), a graphics processing unit (GPU) and a field-programmable gate array (FPGA), or a combination thereof.
11. The apparatus of claim 9 wherein said processor comprises a graphics processing unit (GPU).
12. The apparatus of claim 9 wherein said processor comprises a field-programmable gate array (FPGA).
13. The apparatus of claim 9 wherein said processor comprises a central processing unit (CPU).
14. The apparatus of claim 9 wherein said processor comprises a digital microprocessor.
15. The apparatus of claim 14 wherein said digital microprocessor comprises at least one of a central processing unit (CPU), a graphics processing unit (GPU) GPU, a general-purpose graphics processing unit (GPGPU), a Vector Processor, a Stream Processor or a combination thereof.
16. The apparatus of claim 14 wherein said digital microprocessor comprises a digital computing architecture that performs logical operations over bits in one or more memory spaces.
17. The apparatus of claim 14 wherein said digital microprocessor comprises a Vector Processor.
18. The apparatus of claim 14 wherein said digital microprocessor comprises a Stream Processor.