USB type-C signal interface circuit
View Patent ↗A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D− terminals of a type-C receptacle. A D+/D− multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D− multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.
1. A device comprising a USB-C controller instantiated as a first integrated circuit, the USB-C controller comprising:
a first set of terminals to be coupled to host controllers;
a second set of terminals to be coupled to sets of D+/D− terminals of a type-C receptacle;
a D+/D− multiplexer to selectively couple the first set of terminals to the second set of terminals;
an electrostatic discharge (ESD) protection circuit coupled between the D+/D− multiplexer and the second set of terminals; and
a charger detector circuit coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.
2. The device of claim 1 , wherein the first set of terminals comprises the positive data system terminal and the negative data system terminal coupled to a USB host controller and a data transmitter terminal and data receiver terminal coupled to a proprietary host controller, the second set of terminals comprises first and second positive data terminals coupled to corresponding D+ terminals of the type-C receptacle and first and second negative data terminals coupled to corresponding D− terminals of the type-C receptacle, and wherein the D+/D− multiplexer is to couple:
the positive data system terminal to one of the first and second positive data terminals;
the data transmitter terminal to one of the first and second positive data terminals;
the negative data system terminal to one of the first and second negative data terminals; and
the data receiver terminal to one of the first and second negative data terminals.
3. The device of claim 1 , wherein the first set of terminals comprises a set of Universal Asynchronous Receiver-Transmitter (UART) terminals.
4. The device of claim 1 , wherein the first set of terminals is associated with a first connection of a single USB port, and wherein the second set of terminals is associated with a second connection of the single USB port.
5. The device of claim 1 , wherein the charger detector circuit is further coupled between a data transmitter terminal and a data receiver terminal of the first set of terminals, the charger detector circuit further to detect whether a second positive data terminal and a second negative data terminal of the second set of terminals are coupled to a second USB charger through the type-C receptacle.
6. The device of claim 1 , wherein the ESD protection circuit comprises:
an IEC ESD RC snapback clamp coupled between a local power supply and a ground;
at least one HBM diode coupled between the local power supply and each of the second set of terminals; and
at least one HBM diode coupled between the ground and each of the second set of terminals.
7. The device of claim 1 , wherein the USB-C controller further comprises system ESD protection circuitry comprising:
a first human body model (HBM) snapback clamp coupled to a ground;
a first pair of diodes connected in series and coupled between the first HBM snapback clamp and a positive data system terminal of the first set of terminals;
a second HBM snapback clamp coupled to the ground; and
a second pair of diodes connected in series and coupled between the second HBM snapback clamp and a negative data system terminal of the first set of terminals.
8. The device of claim 1 , wherein the D+/D− multiplexer is controlled to provide flip correction based on a configuration channel (CC) signal.
9. The device of claim 1 , wherein the charger detector circuit includes a first switch coupled to the positive data system terminal and a second switch coupled to the negative data system terminal, the first switch and the second switch controllable by first logic to disconnect the charger detector circuit during high-speed data transfer of the USB-C controller.
10. The device of claim 1 , wherein the USB-C controller further comprises a charge pump coupled to gates of metal-oxide-semiconductor field-effect transistors (MOSFETs) of the D+/D− multiplexer, wherein the charge pump is to drive the MOSFETs to operate such that each MOSFET exhibits less than seven-ohm resistance.
11. A system comprising:
a USB host controller and a proprietary host controller;
a USB type-C receptacle; and
a USB-C controller coupled to the USB type-C receptacle, to the USB host controller, and to the proprietary host controller, the USB-C controller comprising:
a first set of first terminals coupled to the USB host controller;
a second set of terminals coupled to the proprietary host controller;
a third set of terminals to be coupled to sets of D+/D− terminals of the USB type-C receptacle;
a D+/D− multiplexer to selectively couple the first and second sets of terminals to the third set of terminals;
an electrostatic discharge (ESD) protection circuit coupled between the D+/D− multiplexer and the third set of terminals; and
a charger detector circuit coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the third set of terminals is coupled to a USB charger through the type-C receptacle.
12. The system of claim 11 , wherein the first set of terminals comprises the positive data system terminal and the negative data system terminal, the second set of terminals comprises a data transmitter terminal and data receiver terminal, the third set of terminals comprises first and second positive data terminals coupled to corresponding D+ terminals of the type-C receptacle and first and second negative data terminals coupled to corresponding D− terminals of the type-C receptacle, and wherein the D+/D− multiplexer is to couple:
the positive data system terminal to one of the first and second positive data terminals;
the data transmitter terminal to one of the first and second positive data terminals;
the negative data system terminal to one of the first and second negative data terminals; and
the data receiver terminal to one of the first and second negative data terminals.
13. The system of claim 11 , wherein the first set of terminals comprises a set of Universal Asynchronous Receiver-Transmitter (UART) terminals.
14. The system of claim 11 , wherein the first set of terminals is associated with a first connection of a single USB port, and wherein the second set of terminals is associated with a second connection of the single USB port.
15. The system of claim 11 , wherein the ESD protection circuit comprises:
an IEC ESD RC snapback clamp coupled between a local power supply and a ground;
at least one HBM diode coupled between the local power supply and each of the second set of terminals; and
at least one HBM diode coupled between the ground and each of the second set of terminals.
16. The system of claim 11 , wherein the USB-C controller further comprises system ESD protection circuitry comprising:
a first human body model (HBM) snapback clamp coupled to a ground;
a first pair of diodes connected in series and coupled between the first HBM snapback clamp and a positive data system terminal of the first set of terminals;
a second HBM snapback clamp coupled to the ground; and
a second pair of diodes connected in series and coupled between the second HBM snapback clamp and a negative data system terminal of the first set of terminals.
17. The system of claim 11 , wherein the D+/D− multiplexer is controlled to provide flip correction based on a configuration channel (CC) signal.
18. The system of claim 11 , wherein the charger detector circuit includes a first switch coupled to the positive data system terminal and a second switch coupled to the negative data system terminal, the first switch and the second switch controllable by first logic to disconnect the charger detector circuit during high-speed data transfer of the USB-C controller.
19. The system of claim 11 , wherein the USB-C controller further comprises a charge pump coupled to gates of metal-oxide-semiconductor field-effect transistors (MOSFETs) of the D+/D− multiplexer, wherein the charge pump is to drive the MOSFETs to operate such that each MOSFET exhibits less than seven-ohm resistance.
20. A method comprising:
operating a USB-C controller instantiated as a first integrated circuit, wherein the USB-C controller comprises a D+/D− multiplexer, a charger detector circuit, and an electrostatic discharge (ESD) protection circuit, and wherein operating the USB-C controller comprises:
selectively coupling, by the D+/D− multiplexer, a first set of terminals to a second set of terminals, wherein the first set of terminals are coupled to host controllers and the second set of terminals are coupled to sets of D+/D− terminals of a type-C receptacle;
detecting, by the charger detector circuit, whether the second set of terminals are coupled to a USB charger through the type-C receptacle, wherein the charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals; and
providing ESD protection by the ESD protection circuit, wherein the ESD protection circuit is coupled between the D+/D− multiplexer and the second set of terminals.