Long-distance high-speed data and clock transmission
View Patent ↗A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.
1. A transmission line comprising:
a signal path comprising:
a signal propagation medium; and
a termination point along the signal propagation medium; and
an impedance connected at the termination point along the signal path, wherein the impedance comprises a first inverter and a second inverter, wherein a gate electrode of a positive side transistor in the first inverter is connected to a gate electrode of a positive side transistor in the second inverter, and a gate electrode of a negative side transistor in the first inverter is connected to a gate electrode of a negative side transistor in the second inverter.
2. The transmission line of claim 1 , where:
the impedance exhibits properties of a non-linear resistor.
3. The transmission line of claim 1 , where:
the impedance is voltage controlled.
4. The transmission line of claim 1 , where:
the signal path comprises a differential signal path.
5. The transmission line of claim 4 , where:
the impedance is connected across the differential signal path.
6. The transmission line of claim 4 , where:
the differential signal path comprises a first path and a second path;
an input voltage of the impedance comprises a differential voltage comprising a positive component and a negative component; and
the impedance comprises:
the first inverter with a first input configured to receive the positive component of the differential voltage; and
the second inverter with a second input configured to receive the negative component of the differential voltage; where:
the first inverter is connected back-to-back with the second inverter;
the first input is connected to the first path; and
the second input is connected to the second path.
7. A transmission line comprising:
a signal path comprising:
a signal propagation medium; and
a termination point along the signal propagation medium; and
an impedance connected at the termination point along the signal path, wherein the impedance comprises a first inverter and a second inverter, wherein a positive side transistor in the first inverter is connected to a positive side transistor in the second inverter, and a negative side transistor in the first inverter is connected to a negative side transistor in the second inverter; and
a bias circuit comprising:
a reference voltage input configured to be one-half of a supply voltage; and
a calibrated output impedance of the bias circuit connected to the impedance for the bias circuit to configure the impedance according to the reference voltage input.
8. The transmission line of claim 7 , where:
the reference voltage input comprises a positive side reference voltage;
the calibrated output impedance comprises a positive side calibrated output impedance and a negative side calibrated output impedance; and
the bias circuit is connected to the positive side transistor in the first inverter.
9. The transmission line of claim 8 , where:
the reference voltage input comprises a negative side reference voltage;
wherein the bias circuit is further connected to the negative side transistor in the first inverter.
10. A method comprising:
providing a signal path in a circuit, the signal path comprising a signal propagation medium; and
in the circuit, providing an impedance at a termination point along the signal path by placing a first inverter connected back-to-back with a second inverter, wherein a positive side transistor in the first inverter is connected to a positive side transistor in the second inverter, and
a negative side transistor in the first inverter is connected to a negative side transistor in the second inverter, wherein providing the impedance includes:
providing a negative impedance in response to a first range of input voltages, and providing a positive impedance in response to a second range of input voltages.
11. The method of claim 10 , wherein providing the impedance comprises providing a non-linear resistor.
12. The method of claim 11 , wherein the non-linear resistor is a voltage controlled resistor.
13. The method of claim 10 , further comprising:
providing a bias circuit comprising a reference voltage input and a calibrated output impedance connected to the impedance.
14. The method of claim 10 , further comprising:
providing a positive side bias circuit comprising a positive side reference voltage input and a positive side calibrated output impedance connected to the impedance; and
providing a negative side bias circuit comprising a negative side reference voltage input and a negative side calibrated output impedance connected to the impedance.
15. A circuit comprising:
a first circuit;
a second circuit;
a differential signal line connecting the first circuit and the second circuit; and
an impedance connected across the differential signal line, wherein the impedance comprises a first inverter and a second inverter, wherein a gate electrode of a positive side transistor in the first inverter is connected to a gate electrode of a positive side transistor in the second inverter, and a gate electrode of a negative side transistor in the first inverter is connected to a gate electrode of a negative side transistor in the second inverter.
16. The circuit of claim 15 , where:
the first circuit and the second circuit are carried in a multiple-chip module package; and
the first inverter is connected back-to-back with the second inverter.
17. The circuit of claim 15 , where the impedance exhibits properties of a non-linear resistor.
18. The circuit of claim 17 , wherein the non-linear resistor is voltage controlled.
19. The circuit of claim 15 , further comprising:
a bias circuit comprising:
a reference voltage input; and
a calibrated output impedance connected to the impedance.
20. A circuit comprising:
a first circuit;
a second circuit;
a differential signal line connecting the first circuit and the second circuit; and
an impedance connected across the differential signal line, wherein the impedance comprises a first inverter and a second inverter, wherein a positive side transistor in the first inverter is connected to a positive side transistor in the second inverter, and a negative side transistor in the first inverter is connected to a negative side transistor in the second inverter,
wherein the impedance is configured to:
present a negative impedance in response to a first range of input voltages, wherein the first range of input voltages is below a power supply input voltage applied to the impedance; and
present a positive impedance in response to a second range of input voltages,
wherein the second range of input voltages is above the power supply input voltage.