Systems and methods to prevent system crashes due to link failure in memory mirroring mode
View Patent ↗Systems and methods for preventing system crashes due to memory link failure in memory mirroring mode in an information handling system (IHS). The IHS may include a first memory device, a second memory device, and an integrated memory controller (IMC). The IMC may issue write transactions to both the first and second memory devices and issue read transactions to the first memory device when the IMC is in memory mirroring mode. The IMC may transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device. The BIOS may perform a memory mirror failover process that may cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error.
1. An information handling system (IHS), comprising:
a first memory device;
a second memory device; and
a processor including an integrated memory controller (IMC), the IMC configured to:
issue write transactions to both the first memory device and the second memory device when the IMC is in memory mirroring mode;
issue read transactions to the first memory device when the IMC is in memory mirroring mode; and
transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device, the processor configured to execute the BIOS to:
receive the SMI with the IMC error from the IMC;
determine whether i) the IMC is in the memory mirroring mode and ii) the IMC error is a fatal memory link error;
in response to determining that i) the IMC is not in the memory mirroring mode and ii) the IMC error is a fatal memory link error, transmit a machine check error (MCE) interrupt with an uncorrectable error to an operating system (OS) of the IHS;
in response to determining that i) the IMC is in the memory mirroring mode and ii) the IMC error is a fatal memory link error: a) perform a memory mirror failover process to cause the IMC to issue the write transactions and the read transactions to the second memory device, and b) transmit a system control interrupt (SCI) with a memory redundancy lost event to the OS of the IHS independent of transmitting the MCE interrupt to the OS of the HIS.
2. The information handling system of claim 1 , wherein the memory mirror failover process to further cause the IMC to quiesce any outstanding write and read transactions to the first memory device.
3. The information handling system of claim 1 , wherein the first memory device and the second memory device comprise dual in-line memory modules (DIMMs).
4. The information handling system of claim 1 , wherein the information handling system further comprises:
a first memory channel coupled between the IMC and the first memory device; and
a second memory channel coupled between the IMC and the second memory device.
5. The information handling system of claim 1 , wherein the information handling system further comprises:
a first memory channel coupled between the IMC and the first memory device; and
a second memory channel coupled between the IMC and the second memory device, wherein
the IMC communicates with the first memory channel via a first double data rate/double data rate transactional (DDR/DDRT) link, and wherein
the IMC communicates with the second memory channel via a second DDR/DDRT link.
6. The information handling system of claim 1 , wherein the memory mirror redundancy lost event comprises information that describes which DIMM of the first memory device is associated with the fatal memory link error and is to be replaced.
7. The information handling system of claim 1 , wherein the fatal memory link error comprises one of a persistent uncorrectable command error or a persistent uncorrectable address error.
8. A method, comprising:
issuing, by an integrated memory controller (IMC), write transactions to both a first memory device and a second memory device of the IHS when the IMC is in memory mirroring mode;
issuing, by the IMC, read transactions to the first memory device when the IMC is in memory mirroring mode;
transmitting, by the IMC, a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) of the IHS when a persistent uncorrected IMC error is detected within the first memory device;
receiving, by the BIOS, the SMI with the IMC error from the IMC;
determining whether i) the IMC is in the memory mirroring mode and ii) the IMC error is a fatal memory link error;
in response to determining that i) the IMC is not in the memory mirroring mode and ii) the IMC error is a fatal memory link error, transmitting, by the BIOS, a machine check error (MCE) interrupt with an uncorrectable error to an operating system (OS) of the IHS;
in response to determining that i) the IMC is in the memory mirroring mode and ii) the IMC error is a fatal memory link error: a) performing, by the BIOS, a memory mirror failover process to cause the IMC to issue the write transactions and the read transactions to the second memory device, and b) transmitting, by the BIOS, a system control interrupt (SCI) with a memory redundancy lost event to the OS of the IHS independent of transmitting the MCE interrupt to the OS of the HIS.
9. The method of claim 8 , wherein the memory mirror failover process to further cause the IMC to quiesce any outstanding write and read transactions to the first memory device.
10. The method of claim 8 , wherein the first memory device and the second memory device comprise dual in-line memory modules (DIMMs).
11. The method of claim 8 , wherein the information handling system further comprises:
a first memory channel coupled between the IMC and the first memory device; and
a second memory channel coupled between the IMC and the second memory device.
12. The method of claim 8 , wherein the information handling system further comprises:
a first memory channel coupled between the IMC and the first memory device; and
a second memory channel coupled between the IMC and the second memory device, wherein
the IMC communicates with the first memory channel via a first double data rate/double data rate transactional (DDR/DDRT) link, and wherein
the IMC communicates with the second memory channel via a second DDR/DDRT link.
13. The method of claim 8 , wherein the memory mirror redundancy lost event comprises information that describes which DIMM of the first memory device is associated with the fatal memory link error and is to be replaced.
14. The method of claim 8 , wherein the fatal memory link error comprises one of a persistent uncorrectable command error or a persistent uncorrectable address error.