Vertical FET with reduced parasitic capacitance
A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.
1. A method for reducing parasitic capacitance of a semiconductor structure, the method comprising:
forming a first source/drain region under a fin structure;
forming first spacers adjacent the fin structure;
forming second spacers adjacent the first source/drain region;
recessing the first source/drain region in exposed areas; and
depositing a bottom spacer over an STI region formed within the exposed areas of the recessed first source/drain region such that the first spacers adjacent the fin structure are selectively removed before the bottom spacer is deposited over the STI region.
2. The method of claim 1 , wherein the bottom spacer defines a reverse-stepped structural configuration.
3. The method of claim 2 , further comprising forming a metal gate stack over the bottom spacer.
4. The method of claim 3 , wherein the metal gate stack is formed such that gate-to-source/drain capacitances are reduced by extending the STI region between the metal gate stack and the first source/drain region.
5. The method of claim 4 , further comprising depositing a top spacer over the metal gate stack.
6. The method of claim 5 , further comprising cutting the metal gate stack after forming the first spacers.
7. The method of claim 6 , further comprising forming a second source/drain region over the fin structure after cutting the metal gate stack.
8. The method of claim 7 , further comprising forming contacts such that the STI region extends a length between the metal gate stack and the first source/drain region.
9. The method of claim 8 , wherein the STI region covers the second spacers adjacent the first source/drain region in their entirety.
10. The method of claim 9 , wherein a distance between the metal gate stack and the first source/drain region is greater than about 10 nm.
11. A semiconductor structure for reducing parasitic capacitance, the structure comprising:
a first source/drain region disposed under a fin structure;
first spacers disposed adjacent the fin structure;
second spacers disposed adjacent the first source/drain region;
exposed areas created by recessing the first source/drain region; and
a bottom spacer deposited over an STI region formed within the exposed areas of the recessed first source/drain region such that the first spacers adjacent the fin structure are selectively removed before the bottom spacer is deposited over the STI region.
12. The structure of claim 11 , wherein the bottom spacer defines a reverse-stepped structural configuration.
13. The structure of claim 12 , wherein a metal gate stack is disposed over the bottom spacer.
14. The structure of claim 13 , wherein the metal gate stack is disposed such that gate-to-source/drain capacitances are reduced by extending the STI region between the metal gate stack and the first source/drain region.
15. The structure of claim 14 , wherein a top spacer is disposed over the metal gate stack.
16. The structure of claim 15 , wherein the metal gate stack is cut after forming the first spacers.
17. The structure of claim 16 , wherein a second source/drain region is disposed over the fin structure after cutting the metal gate stack.
18. The structure of claim 17 , wherein contacts are created such that the STI region extends a length between the metal gate stack and the first source/drain region.
19. The structure of claim 18 , wherein the STI region covers the second spacers adjacent the first source/drain region in their entirety.
20. The structure of claim 19 , wherein a distance between the metal gate stack and the first source/drain region is greater than about 10 nm.