IP Library Granted Patent US 10,303,597
Granted Patent B2
US 10,303,597 · App. 16/010,583 · Granted May 28, 2019

Computing device, data transfer method between coprocessor and non-volatile memory, and computer-readable recording medium

Inventor: Myoungsoo Jung (Incheon, KR)
Assignees: MEMRAY CORPORATION; YONSEI UNIVERSITY, UNIVERSITY—INDUSTRY FOUNDATION (UIF)
G06F12/023G06F12/063G06F13/4068G06F2212/1024G06F2212/205G06F2212/206G06F2212/214G06F2212/251G06F2212/7201G06F2212/7202
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Quick Facts
Patent No.
US 10,303,597
App. No.
16/010,583
Granted
May 28, 2019
Kind
B2
Abstract

A computing device includes a CPU, a CPU memory for CPU, a non-volatile memory, a coprocessor using the non-volatile memory, a coprocessor memory for storing data to be processed by the coprocessor or data processed by the coprocessor, and a recording medium. The recording medium includes a controller driver for the non-volatile memory and a library that are executed by the CPU. The controller driver maps the coprocessor memory to a system memory block of the CPU memory. The library moves data between the coprocessor and the non-volatile memory via the system memory block mapped to the coprocessor memory.

Claims (30)

1. A memory management device for a computing device including a central processing unit (CPU), a non-volatile memory used as a storage, a coprocessor, and a coprocessor memory that stores data to be processed by the coprocessor or data processed by the coprocessor, the memory management device comprising:

a controller driver that exposes a memory space used by the CPU to the coprocessor memory; and

a library that moves the data to be processed by the coprocessor or the data processed by the coprocessor between the coprocessor and the non-volatile memory via the memory space exposed to the coprocessor memory,

wherein the controller driver manages a register which includes a plurality of entries for pointing addresses of the memory space.

2. The memory management device of claim 1 , wherein each entry points a logical block address of a space with a predetermined size in the memory space, and the logical block address corresponds to a physical block address of a space with a predetermined size in the coprocessor memory.

3. The memory management device of claim 2 , wherein, when the coprocessor reads read data from the non-volatile memory, the controller driver transfers the read data from the non-volatile memory to the space of the physical block address that corresponds to the logical block address pointed by a corresponding entry among the entries.

4. The memory management device of claim 2 , wherein the computing device further includes a CPU memory used by the CPU, and the register is stored in a memory used by the CPU.

5. The memory management device of claim 1 , wherein the library resides on top of a native file system in a software stack.

6. The memory management device of claim 1 , wherein the computing device further includes a CPU memory used by the CPU, and

wherein the memory space is appended to the CPU memory.

7. A memory management device for a computing device including a central processing unit (CPU), a non-volatile memory used as a storage, a coprocessor, and a coprocessor memory that stores data to be processed by the coprocessor or data processed by the coprocessor, the memory management device comprising:

a controller driver that manages a plurality of entries for pointing a system memory area used by the CPU, wherein each of the entries points a logical block address of a space with a predetermined size in the system memory area, and the logical block address corresponds to a physical block address of a space with a predetermined size in the coprocessor memory; and

a library that moves the data to be processed by the coprocessor or the data processed by the coprocessor between the coprocessor and the non-volatile memory via the system memory area.

8. The memory management device of claim 7 , wherein, when the coprocessor reads read data from the non-volatile memory, the controller driver transfers the read data from the non-volatile memory to the space of the physical block address that corresponds to the logical block address pointed by a corresponding entry among the entries.

9. The memory management device of claim 7 , wherein the library resides on top of a native file system in a software stack.

10. A non-transitory computer-readable recording medium that stores a program to be executed by a computing device including a central processing unit (CPU), a non-volatile memory used as a storage, a coprocessor, and a coprocessor memory that stores data to be processed by the coprocessor or data processed by the coprocessor, the program comprising:

a controller driver that exposes a memory space used by the CPU to the coprocessor memory; and

a library that moves the data to be processed by the coprocessor or the data processed by the coprocessor between the coprocessor and the non-volatile memory via the memory space exposed to the coprocessor memory,

wherein the controller driver manages a register which includes a plurality of entries for pointing addresses of the memory space.

11. The non-transitory computer-readable recording medium of claim 10 , wherein each entry points a logical block address of a space with a predetermined size in the memory space, and the logical block address corresponds to a physical block address of a space with a predetermined size in the coprocessor memory.

12. The non-transitory computer-readable recording medium of claim 11 , wherein, when the coprocessor reads read data from the non-volatile memory, the controller driver transfers the read data from the non-volatile memory to the space of the physical block address that corresponds to the logical block address pointed by a corresponding entry among the entries.

13. The non-transitory computer-readable recording medium of claim 11 , wherein the computing device further includes a CPU memory used by the CPU, and the register is stored in a memory used by the CPU.

14. The non-transitory computer-readable recording medium of claim 10 , wherein the library resides on top of a native file system in a software stack.

15. The non-transitory computer-readable recording medium of claim 10 , wherein the computing device further includes a CPU memory used by the CPU, and

wherein the memory space is appended to the CPU memory.

16. A non-transitory computer-readable recording medium that stores a program to be executed by a computing device including a central processing unit (CPU), a non-volatile memory used as a storage, a coprocessor, and a coprocessor memory that stores data to be processed by the coprocessor or data processed by the coprocessor, the program comprising:

a controller driver that manages a plurality of entries for pointing a system memory area used by the CPU, wherein each of the entries points a logical block address of a space with a predetermined size in the memory space, and the logical block address corresponds to a physical block address of a space with a predetermined size in the coprocessor memory; and

a library that moves the data to be processed by the coprocessor or the data processed by the coprocessor between the coprocessor and the non-volatile memory via the system memory area.

17. The non-transitory computer-readable recording medium of claim 16 , wherein, when the coprocessor reads read data from the non-volatile memory, the controller driver transfers the read data from the non-volatile memory to the space of the physical block address that corresponds to the logical block address pointed by a corresponding entry among the entries.

18. The non-transitory computer-readable recording medium of claim 16 , wherein the library resides on top of a native file system in a software stack.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2025
From: JUNG, MYOUNGSOO
To: MEMRAY CORPORATION; YONSEI UNIVERSITY, UNIVERSITY – INDUSTRY FOUNDATION (UIF)
Reel/Frame 071922/0364 →
SECURITY INTEREST Recorded Jul 29, 2025
From: MEMRAY MT LLC
To: PLF 2025-A LP
Reel/Frame 071862/0485 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: YONSEI UNIVERSITY, UNIVERSITY – INDUSTRY FOUNDATION (UIF)
To: MEMRAY CORPORATION
Reel/Frame 071789/0533 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: MEMRAY CORPORATION
To: MEMRAY MT L.L.C
Reel/Frame 071789/0672 →
Priority Claims (1)
KR 10-2016-0017233 · Feb 15, 2016 · national
Continuity (2)
Continuation 15168423 · May 31, 2016
Related Publication 20180300230A1 · Oct 18, 2018