Method and system for an analog-to-digital converter with near-constant common mode voltage
View Patent ↗Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each input line to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2 x where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V ADC _ fs /128+V ADC _ fs /256+V ADC _ fs /512+V ADC _ fs /1024 when m equals 4 and where V ADC _ fs is the full-scale voltage of the ADC.
1. A method for communication, the method comprising:
in an analog-to-digital converter (ADC) comprising a sampling switch, N double-sided switched capacitors, and M single-sided switched capacitors on each input line to the ADC:
sampling an input voltage by closing the sampling switch;
opening the sampling switch and comparing voltage levels between the input lines;
iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground based on the compared voltage levels; and
iteratively switching the single-sided switched capacitors between ground and voltages that are less than Vref.
2. The method according to claim 1 , wherein the voltages that are less than Vref equal Vref/2 x where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line.
3. The method according to claim 2 , wherein a magnitude of a common mode offset of the ADC is less than V ADC _ fs /128+V ADC —fs /256+V ADC —fs /512+V ADC _ fs /1024 when m equals 4 and where V ADC _ fs is a full-scale voltage of the ADC.
4. The method according to claim 1 , comprising controlling the single-sided switched capacitors and the double-sided switched capacitors utilizing successive approximation register (SAR) logic.
5. The method according to claim 4 , comprising comparing the voltage levels utilizing a comparator.
6. The method according to claim 5 , wherein outputs of the comparator are coupled to the SAR logic.
7. The method according to claim 1 , comprising controlling the sampling switch utilizing bootstrapping circuits.
8. The method according to claim 1 , wherein capacitance values of the double-sided switched capacitors are binary coded.
9. The method according to claim 1 , comprising determining the most significant bit (MSB) using one of the double-sided switched capacitors.
10. The method according to claim 1 , comprising determining the least significant bit (LSB) using one of the single-sided switched capacitors.
11. A system for communication, the system comprising:
one or more circuits comprising an analog-to-digital converter (ADC) comprising a sampling switch, N double-sided switched capacitors, and M single-sided switched capacitors on each input line to the ADC, said one or more circuits being operable to:
sample an input voltage by closing the sampling switch;
open the sampling switch and compare voltage levels between the input lines;
iteratively switch the double-sided switched capacitors between a reference voltage (Vref) and ground based on the compared voltage levels; and
iteratively switch the single-sided switched capacitors between ground and voltages that are less than Vref.
12. The system according to claim 11 , wherein the voltages that are less than Vref equal Vref/2 x where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line.
13. The system according to claim 12 , wherein a magnitude of a common mode offset of the ADC is less than V ADC _ fs /128+V ADC —fs /256+V ADC —fs /512+V ADC _ fs /1024 when m equals 4 and where V ADC _ fs is a full-scale voltage of the ADC.
14. The system according to claim 11 , wherein said one or more circuits are operable to control the single-sided switched capacitors and the double-sided switched capacitors utilizing successive approximation register (SAR) logic.
15. The system according to claim 14 , wherein said one or more circuits are operable to compare the voltage levels utilizing a comparator.
16. The system according to claim 15 , wherein outputs of the comparator are coupled to the SAR logic.
17. The system according to claim 11 , wherein said one or more circuits are operable to control the sampling switch utilizing bootstrapping circuits.
18. The system according to claim 11 , wherein capacitance values of the double-sided switched capacitors are binary coded.
19. The system according to claim 11 , wherein said one or more circuits are operable to determine the most significant bit (MSB) using one of the double-sided switched capacitors and determine the least significant bit (LSB) using one of the single-sided switched capacitors.
20. A system for communication, the system comprising:
one or more circuits comprising an analog-to-digital converter (ADC) comprising a sampling switch, a comparator, N double-sided switched capacitors, and M single-sided switched capacitors on each input line to the ADC, said one or more circuits being operable to:
sample an input voltage by closing the sampling switch;
open the sampling switch and compare voltage levels between the input lines utilizing the comparator;
iteratively switch the double-sided switched capacitors between a reference voltage (Vref) and ground and compare voltage levels between the input lines utilizing the comparator; and
iteratively switch the single-sided switched capacitors between ground and voltages that are less than Vref and compare voltage levels between the input lines utilizing the comparator.