Automated resetting of storage devices and remote reporting of assert logs

1. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:

send, by a storage device, a challenge request to a remote system, wherein the challenge request is sent in response to a local de-assert request,

receive, by the storage device, a challenge response from the remote system,

conduct, by the storage device, a validity analysis of the challenge response,

conduct, by the storage device, a state analysis of the storage device based on an assert log associated with a failure condition in the storage device, wherein the state analysis is conducted in response to the validity analysis being successful,

return, by the storage device, the storage device to service if the state analysis indicates that the storage device is operable, wherein the logic coupled to the one or more substrates is to preserve one or more counter values in the storage device during the return of the storage device to service, and

remove, by the storage device, the storage device from service if the state analysis indicates that the storage device is inoperable.

2. The semiconductor apparatus of claim 1 , wherein the logic coupled to the one or more substrates is to:

generate, by the storage device, an encryption key,

encrypt, by the storage device, the assert log with the encryption key,

encrypt, by the storage device, the encryption key with a public key associated with the assert log, and

send, by the storage device, the encrypted encryption key and the encrypted assert log to the remote system.

3. The semiconductor apparatus of claim 2 , wherein the encryption key is generated based on a random number generator output.

4. The semiconductor apparatus of claim 1 , wherein the assert log is to include one or more of an assert condition, a memory dump, a serial number, fuse information or temperature information.

5. A system comprising:

a host processor;

a network controller; and

a storage device including a memory array and a memory controller coupled to the memory array, the memory controller including logic to:

conduct a state analysis of the storage device based on an assert log associated with a failure condition in the storage device, wherein the state analysis is conducted in response to a validity analysis of a challenge response being successful,

return the storage device to service if the state analysis indicates that the storage device is operable, and

remove the storage device from service if the state analysis indicates that the storage device is inoperable.

6. The system of claim 5 , wherein the logic coupled to the one or more substrates is to:

send the challenge request to a remote system,

receive the challenge response from the remote system, and

conduct a validity analysis of the challenge response, wherein the state analysis is conducted in response to the validity analysis being successful.

7. The system of claim 6 , wherein the challenge request is sent in response to a local de-assert request.

8. The system of claim 5 , wherein the logic coupled to the one or more substrates is to:

generate an encryption key,

encrypt the assert log with the encryption key,

encrypt the encryption key with a public key associated with the assert log, and

send the encrypted encryption key and the encrypted assert log to a remote system.

9. The system of claim 8 , wherein the encryption key is generated based on a random number generator output.

10. The system of claim 5 , wherein the logic coupled to the one or more substrates is to preserve one or more counter values in the storage device during the return of the storage device to service.

11. The system of claim 5 , wherein the assert log is to include one or more of an assert condition, a memory dump, a serial number, fuse information or temperature information.

12. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:

conduct, by a storage device, a state analysis of the storage device based on an assert log associated with a failure condition in the storage device, wherein the state analysis is conducted in response to a validity analysis of a challenge response being successful,

return, by the storage device, the storage device to service if the state analysis indicates that the storage device is operable, and

remove, by the storage device, the storage device from service if the state analysis indicates that the storage device is inoperable.

13. The semiconductor apparatus of claim 12 , wherein the logic coupled to the one or more substrates is to:

send, by the storage device, the challenge request to a remote system,

receive, by the storage device, the challenge response from the remote system, and

conduct, by the storage device, a validity analysis of the challenge response, wherein the state analysis is conducted in response to the validity analysis being successful.

14. The semiconductor apparatus of claim 13 , wherein the challenge request is sent in response to a local de-assert request.

15. The semiconductor apparatus of claim 12 , wherein the logic coupled to the one or more substrates is to:

generate, by the storage device, an encryption key,

encrypt, by the storage device, the assert log with the encryption key,

encrypt, by the storage device, the encryption key with a public key associated with the assert log, and

send, by the storage device, the encrypted encryption key and the encrypted assert log to a remote system.

16. The semiconductor apparatus of claim 15 , wherein the encryption key is generated based on a random number generator output.

17. The semiconductor apparatus of claim 12 , wherein the logic coupled to the one or more substrates is to preserve one or more counter values in the storage device during the return of the storage device to service.

18. The semiconductor apparatus of claim 12 , wherein the assert log is to include one or more of an assert condition, a memory dump, a serial number, fuse information or temperature information.

19. A method comprising:

conducting, by a storage device, a state analysis of the storage device based on an assert log associated with a failure condition in the storage device, wherein the state analysis is conducted in response to a validity analysis of a challenge response being successful;

returning, by the storage device, the storage device to service if the state analysis indicates that the storage device is operable; and

removing, by the storage device, the storage device from service if the state analysis indicates that the storage device is inoperable.

20. The method of claim 19 , further including:

sending, by the storage device, the challenge request to a remote system;

receiving, by the storage device, the challenge response from the remote system; and

conducting, by the storage device, a validity analysis of the challenge response, wherein the state analysis is conducted in response to the validity analysis being successful.