Noise-shaping analog-to-digital converter

1. A method of operating a noise-shaping successive approximation register analog-to-digital converter (ADC) circuit including time-interleaved signal acquisition with a shared noise-shaping circuit, the method comprising:

receiving at a first rate, using a first digital-to-analog converter (DAC) circuit, a first sample of an input signal during an acquisition phase of the first DAC circuit;

receiving at the first rate, using a second DAC circuit, a second sample of the input signal during an acquisition phase of the second DAC circuit that occurs after the acquisition phase of the first DAC circuit;

combining a residue charge of the first DAC circuit and a residue charge of the second DAC circuit;

updating the noise-shaping circuit at a second rate less than the first rate;

generating an output using the combination of residue charge; and

controlling a timing between the first and second DAC circuits and the noise-shaping circuit to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits.

2. The method of claim 1 , comprising:

receiving the residue charge of the first DAC circuit after a bit-trial phase of the first DAC circuit; and

receiving the residue charge of the second DAC circuit after a bit-trial phase of the second DAC circuit.

3. The method of claim 1 , comprising:

sharing the noise-shaping circuit between the first and second DAC circuits.

4. The method of claim 1 , wherein controlling a timing between the first and second DAC circuits to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits includes:

controlling a first plurality of switches such that the first DAC circuit receives a first sample of an input signal during an acquisition phase of the first DAC circuit; and

controlling a second plurality of switches such that the second DAC circuit receives a second sample of the input signal during an acquisition phase of the second DAC circuit that occurs after the acquisition phase of the first DAC circuit.

5. The method of claim 1 , further comprising:

receiving at the first rate, using a third DAC circuit, a third sample of the input signal during an acquisition phase of the third DAC circuit that occurs after the acquisition phases of the first and second DAC circuits; and

wherein controlling a timing between the first and second DAC circuits to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits includes:

controlling a timing between the first, second, and third DAC circuits to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first, second, and third DAC circuits.

6. The method of claim 5 , comprising:

receiving the residue charge of the first DAC circuit after a bit-trial phase of the first DAC circuit;

receiving the residue charge of the second DAC circuit after a bit-trial phase of the second DAC circuit;

receiving the residue charge of the third DAC circuit after a bit-trial phase of the third DAC circuit; and

combining the residue charge of the third DAC circuit with the residue charges of the first and second DAC circuits.

7. The method of claim 5 , wherein controlling a timing between the first, second, and third DAC circuits to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first, second, and third DAC circuits is such that:

the time-interleaving includes the first DAC circuit performing a bit-trial on the first sample of the input signal during the acquisition phase of the second DAC circuit that occurs during a residue charge transfer phase of the third DAC circuit.

8. A noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) circuit including time-interleaved signal acquisition with a shared noise-shaping circuit, the ADC circuit comprising:

a first digital-to-analog converter (DAC) circuit configured to receive, at a first rate, a first sample of an input signal during an acquisition phase of the first DAC circuit;

a second DAC circuit configured to receive, at the first rate, a second sample of the input signal during an acquisition phase of the second DAC circuit that occurs after the acquisition phase of the first DAC circuit;

a control circuit configured to:

control a timing between the first and second DAC circuits and the noise-shaping circuit to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits; and

update the noise-shaping circuit at a second rate less than the first rate; and

the noise-shaping circuit configured to:

combine a residue charge of the first DAC circuit and a residue charge of the second DAC circuit; and

generate an output using the combination of residue charge.

9. The noise-shaping ADC circuit of claim 8 , wherein the noise-shaping circuit is configured to:

receive the residue charge of the first DAC circuit after a bit-trial phase of the first DAC circuit; and

receive the residue charge of the second DAC circuit after a bit-trial phase of the second DAC circuit.

10. The noise-shaping ADC circuit of claim 8 , wherein the noise-shaping circuit is shared by the first and second DAC circuits.

11. The noise-shaping ADC circuit of claim 8 ,

wherein the first DAC circuit includes a first plurality of switches;

wherein the second DAC circuit includes a second plurality of switches; and

wherein the control circuit configured to control a timing between the first and second DAC circuits to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits is configured to:

control the first plurality of switches such that the first DAC circuit receives a first sample of an input signal during an acquisition phase of the first DAC circuit; and

control the second plurality of switches such that the second DAC circuit receives a second sample of the input signal during an acquisition phase of the second DAC circuit that occurs after the acquisition phase of the first DAC circuit.

12. The noise-shaping ADC circuit of claim 8 , further comprising:

a third DAC circuit configured to receive, at the first rate, a third sample of the input signal during an acquisition phase of the third DAC circuit,

wherein the control circuit configured to control a timing between the first and second DAC circuits to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits is configured to:

control a timing between the first, second, and third DAC circuits to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first, second, and third DAC circuits.

13. The noise-shaping ADC circuit of claim 12 , wherein the noise-shaping circuit is configured to:

receive the residue charge of the first DAC circuit after a bit-trial phase of the first DAC circuit;

receive the residue charge of the second DAC circuit after a bit-trial phase of the second DAC circuit;

receive the residue charge of the third DAC circuit after a bit-trial phase of the third DAC circuit; and

combine the residue charge of the third DAC circuit with the residue charges of the first and second DAC circuits.

14. The noise-shaping ADC circuit of claim 13 , wherein the noise-shaping circuit is shared by the first, second, and third DAC circuits.

15. The noise-shaping ADC circuit of claim 8 , wherein the noise-shaping circuit includes at least one integrator circuit.

16. The noise-shaping ADC circuit of claim 8 , wherein the control circuit configured to control a timing between the first and second DAC circuits to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits is further configured such that:

the time-interleaving includes the first DAC circuit configured to perform a bit-trial on a first sample of an input signal during an acquisition phase of the second DAC circuit that occurs during a residue charge transfer phase of a third DAC circuit.

17. The noise-shaping ADC circuit of claim 8 , wherein the first and second DAC circuits form a first DAC circuit set, the noise-shaping SAR ADC circuit further comprising:

a second DAC circuit set, wherein the first and second DAC circuit sets are arranged in a differential configuration.

18. A noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) circuit including time-interleaved signal acquisition with a shared noise-shaping circuit, the ADC circuit comprising:

means for receiving at a first rate a first sample of an input signal during an acquisition phase of a first digital-to-analog converter (DAC) circuit;

means for receiving at the first rate a second sample of the input signal during an acquisition phase of a second DAC circuit that occurs after the acquisition phase of the first DAC circuit;

means for combining a residue charge of the first DAC circuit and a residue charge of the second DAC circuit;

means for updating the noise-shaping circuit at a second rate less than the first rate;

means for generating an output using the combination of residue charge; and

means for controlling a timing between the first and second DAC circuits and the noise-shaping circuit to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits.

19. The noise-shaping ADC circuit of claim 18 , comprising:

means for receiving the residue charge of the first DAC circuit after a bit-trial phase of the first DAC circuit; and

means for receiving the residue charge of the second DAC circuit after a bit-trial phase of the second DAC circuit.

20. The noise-shaping ADC circuit of claim 18 , further comprising:

means for receiving a third sample of the input signal during an acquisition phase of a third DAC circuit that occurs after the acquisition phase of the second DAC circuit;

means for receiving at the first rate a residue charge of the first DAC circuit after a bit-trial phase of the first DAC circuit;

means for receiving the residue charge of the second DAC circuit after a bit-trial phase of the second DAC circuit;

means for receiving the residue charge of the third DAC circuit after a bit-trial phase of the third DAC circuit; and

means for combining the residue charges of the first, second, and third DAC circuits.