Write leveling a memory device

1. A memory device, comprising:

a command interface configured to receive write commands from a host device;

an input-output interface configured to receive a data strobe from the host device; and

internal write circuitry configured to launch an internal write signal based at least in part on the write commands, wherein the launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device, wherein the internal write circuitry comprises a plurality of flip-flops, wherein each flip-flop of the plurality of flip-flops is configured to output a potential launched write signal, wherein each flip-flop of the plurality of flip-flops is configured to receive a respective potential launched write signal, and the internal write circuitry comprises selection circuitry configured to select a launched write signal from the potential launched write signals.

2. The memory device of claim 1 , wherein the internal write circuitry comprises the plurality of flip-flops configured to shift an incoming write command output from a portion of a CWL shifter of the memory device.

3. The memory device of claim 2 , wherein a number of the plurality of flip-flops corresponds to a maximum number of cycles before the CWL that the internal write signal can be launched using the internal write circuitry.

4. The memory device of claim 1 , comprising receiving the indication from the host device.

5. The memory device of claim 4 , wherein receiving the indication from the host device comprises receiving the indication at a mode register of the memory device.

6. The memory device of claim 1 , wherein the selection circuitry comprises a first stage of gates and a second stage of gates.

7. The memory device of claim 6 , wherein the second stage of gates receives an output from each gate of the first stage of gates.

8. The memory device of claim 6 , wherein each gate of the first stage of gates receives a respective potential launched write signal and a control signal.

9. The memory device of claim 8 , wherein the internal write circuitry comprises decoder circuitry that is configured to decode the control signals from the indication.

10. A method, comprising:

outputting a clock;

outputting a data strobe signal;

synchronizing the clock and the data strobe signal at a pin of a memory device as an external write leveling operation;

determining a number of cycles to cause the memory device to launch an internal write signal as an internal write leveling operation to cause capture of the internal write signal at a location relative to the data strobe signal, wherein determining the number of cycles comprises:

initially writing a cycle number to the memory device;

sending a write command after initially writing the cycle number;

receiving an indication of whether the write command was successfully captured; and

if the write command was successfully captured, determining that the number is the cycle number;

sending the number of cycles to the memory device; and

adjusting the data strobe signal by less than a cycle as a fine adjustment.

11. The method of claim 10 , wherein the location comprises a first edge of the data strobe signal.

12. The method of claim 10 , wherein determining the number of cycles comprises, for each unsuccessful capture of the write command:

increment the cycle number;

resend the write command after incrementing the cycle number; and

receiving an indication of whether the write command was successfully captured.

13. The method of claim 10 , wherein the fine adjustment comprises:

incrementally shifting the data strobe signal in a first direction until a capture failure occurs; and

after the capture failure occurs, shifting the data strobe signal in a second direction by a half cycle, wherein the second direction is in an opposite direction of the first direction.

14. The method of claim 13 , wherein the first direction comprises a negative-shift direction and the second direction comprises a positive-shift direction.

15. A method comprising:

receiving, at a memory device and from a host device, a data strobe and a clock;

receiving, at the memory device and from the host device, a first write command;

attempting to capture the first write command in the memory device;

from the memory device to the host device, sending an indication that the first write command is captured successfully;

receiving, at the memory device and from the host device, a first shift of the data strobe by the host device;

receiving, at the memory device and from the host device, a second write command;

attempting to capture the second write command in the memory device;

from the memory device to the host device, sending an indication that the second write command capture has failed; and

in response to sending the indication that the second write command capture has failed, receiving a second shift of the data strobe by the host device in a direction opposite of the first shift.

16. The method of claim 15 , comprising:

sending an indication that the first write command has not been captured successfully when attempting to capture the first write command fails; and

re-receiving the first write command one or more times until the first write command is successfully captured.

17. The method of claim 15 , comprising:

sending an indication that the second write command has been captured successfully when attempting to capture the second write command succeeds; and

receiving one or more subsequent write commands until a subsequent write command of the one or more subsequent write commands is successfully captured.