Display device
A display device includes: a plurality of sub-pixels each including a memory block; a clock signal output circuit configured to output a plurality of clock signals having different frequencies; a selection circuit configured to select one of the clock signals as a selected clock signal; a plurality of memory selection line groups provided for respective rows; a memory selection circuit configured to output a memory selection signal concurrently to the memory selection line groups in synchronization with the selected clock signal, the memory selection signal being a signal for selecting one from a plurality of memories in each of the memory blocks; a common electrode to which a common potential common to the sub-pixels is supplied; and a common-electrode driving circuit configured to switch the common potential in synchronization with the reference clock signal and output the switched common potential.
1. A display device comprising:
a plurality of sub-pixels arranged in a row direction and a column direction and each including a first switch circuit, a sub-pixel electrode, and a memory block that includes a plurality of memories each of which is configured to store therein sub-pixel data;
a clock signal output circuit configured to, based on a reference clock signal, output a plurality of clock signals having different frequencies;
a selection circuit configured to select one of the clock signals as a selected clock signal;
a plurality of memory selection line groups provided for respective rows and each including a plurality of memory selection lines electrically coupled to the memory blocks in the respective sub-pixels that belong to the corresponding row;
a memory selection circuit configured to output a memory selection signal concurrently to the memory selection line groups in synchronization with the selected clock signal, the memory selection signal being a signal for selecting one from the memories in each of the memory blocks;
a common electrode to which a common potential common to the sub-pixels is supplied; and
a common-electrode driving circuit configured to switch the common potential in synchronization with the reference clock signal and output the switched common potential,
wherein the first switch circuit of each of the sub-pixels is configured to select one of the memories of the memory block corresponding to the memory selection line that has been supplied with the memory selection signal, and
wherein the sub-pixel electrode is driven based on the sub-pixel data stored in the selected one of the memories to display an image.
2. The display device according to claim 1 ,
wherein each of the sub-pixels further includes
a second switch circuit configured to output a selected display signal to the sub-pixel electrode based on the sub-pixel data received from the memory block via the first switch circuit,
wherein the display device further comprises:
a plurality of display signal lines provided corresponding to the rows and each of which is electrically coupled to the corresponding second switch circuits; and
an inversion driving circuit configured to generate a plurality of display signals including a non-inverted display signal and an inverted display signal obtained by inverting the non-inverted display signal in synchronization with the reference clock signal and output the generated display signals to the display signal lines, and
wherein each of the second switch circuits is configured to output one of the generated display signals as the selected display signal to the sub-pixel electrode based on the sub-pixel data.
3. The display device according to claim 1 ,
wherein the clock signal output circuit outputs, to the selection circuit, the clock signals obtained by dividing the frequency of the reference clock signal by a plurality of division factors.
4. The display device according to claim 1 ,
wherein the memory selection circuit sequentially switches a destination to which the memory selection signal is to be output, from one memory to another among the memory selection lines in each of the memory selection line groups, and
wherein, in accordance with the sequential switching of the destination to which the memory selection signal is to be output, the sub-pixels display an image based on the sub-pixel data stored in the memories.
5. The display device according to claim 1 , further comprising:
a plurality of gate line groups provided for the respective rows and each including a plurality of gate lines electrically coupled to the memory blocks in the respective sub-pixels that belong to the corresponding row;
a gate line driving circuit configured to sequentially output a gate signal to the rows in writing the sub-pixel data into the memory blocks, the gate signal being a signal for selecting one of the rows;
a plurality of source lines provided for respective columns;
a source line driving circuit configured to output a plurality of pieces of the sub-pixel data to the respective source lines in writing the sub-pixel data into the memory blocks; and
a gate line selection circuit configured to electrically couple one of the gate lines in each of the gate line groups to the gate line driving circuit in writing the sub-pixel data into the memory blocks,
wherein each of the sub-pixels further includes a third switch circuit, and
wherein the third switch circuit of each of the sub-pixels in one of the rows that has the gate signal supplied thereto causes the sub-pixel data supplied to the corresponding source line to be stored in one of the memories therein in accordance with the gate line that has been supplied with the gate signal.
6. The display device according to claim 5 ,
wherein, in each of the sub-pixels, the sub-pixel electrode is driven based on the sub-pixel data stored in a first memory of the sub-pixel, in accordance with the memory selection line that has been supplied with the memory selection signal, and at the same time, the third switch circuit stores the sub-pixel data that has been supplied to the corresponding source line in a second memory of the sub-pixel, in accordance with the gate line that has been supplied with the gate signal, and
wherein the first memory is one of the memories of the sub-pixel, and the second memory is different from the first memory.
7. A display device comprising:
a plurality of sub-pixels arranged in a row direction and a column direction and each including a first switch circuit, a sub-pixel electrode, and a memory block that includes a plurality of memories each of which is configured to store therein sub-pixel data;
a clock signal output circuit configured to, based on a reference clock signal, output a plurality of clock signals having different frequencies;
a selection circuit configured to select one of the clock signals as a first selected clock signal and select one of the clock signals as a second selected clock signal;
a plurality of memory selection line groups provided for respective rows and each including a plurality of memory selection lines electrically coupled to the memory blocks in the respective sub-pixels that belong to the corresponding row;
a memory selection circuit configured to output a memory selection signal concurrently to the memory selection line groups in synchronization with the first selected clock signal, the memory selection signal being a signal for selecting one from the memories in each of the memory blocks;
a common electrode to which a common potential common to the sub-pixels is supplied; and
a common-electrode driving circuit configured to switch the common potential in synchronization with the second selected clock signal and output the switched common potential,
wherein the first switch circuit of each of the sub-pixels is configured to select one of the memories of the memory block corresponding to the memory selection line that has been supplied with the memory selection signal, and
wherein the sub-pixel electrode is driven based on the sub-pixel data stored in the selected one of the memories to display an image.
8. The display device according to claim 7 , wherein
wherein each of the sub-pixels further includes
a second switch circuit configured to output a selected display signal to the sub-pixel electrode based on the sub-pixel data received from the memory block via the first switch circuit,
wherein the display device further comprises:
a plurality of display signal lines provided for the rows and each of which is electrically coupled to the corresponding second switch circuits; and
an inversion driving circuit configured to generate a plurality of display signals including a non-inverted display signal and an inverted display signal obtained by inverting the non-inverted display signal in synchronization with the second selected clock signal and output the generated display signals to the display signal lines, and
wherein each of the second switch circuit is configured to output one of the generated display signals as the selected display signal to the sub-pixel electrode based on the sub-pixel data.
9. The display device according to claim 7 ,
wherein the clock signal output circuit outputs, to the selection circuit, the clock signals obtained by dividing the frequency of the reference clock signal by a plurality of division factors.
10. The display device according to claim 7 ,
wherein the memory selection circuit sequentially switches a destination to which the memory selection signal is to be output, from one memory to another among the memory selection lines in each of the memory selection line groups, and
wherein, in accordance with the sequential switching of the destination to which the memory selection signal is to be output, the sub-pixels display an image based on the sub-pixel data stored in the memories.
11. The display device according to claim 7 , further comprising:
a plurality of gate line groups provided for the respective rows and each including a plurality of gate lines electrically coupled to the memory blocks in the respective sub-pixels that belong to the corresponding row;
a gate line driving circuit configured to sequentially output a gate signal to the rows in writing the sub-pixel data into the memory blocks, the gate signal being a signal for selecting one of the rows;
a plurality of source lines provided for respective columns;
a source line driving circuit configured to output a plurality of pieces of the sub-pixel data to the respective source lines in writing the sub-pixel data into the memory blocks; and
a gate line selection circuit configured to electrically couple one of the gate lines in each of the gate line groups to the gate line driving circuit in writing the sub-pixel data into the memory blocks,
wherein each of the sub-pixels further includes a third switch circuit, and
wherein the third switch circuit of each of the sub-pixels in one of the rows that has the gate signal supplied thereto causes the sub-pixel data supplied to the corresponding source line to be stored in one of the memories therein in accordance with the gate line that has been supplied with the gate signal.
12. The display device according to claim 11 ,
wherein, in each of the sub-pixels, the sub-pixel electrode is driven based on the sub-pixel data stored in a first memory of the sub-pixel, in accordance with the memory selection line that has been supplied with the memory selection signal, and at the same time, the third switch circuit stores the sub-pixel data that has been supplied to the corresponding source line in a second memory of the sub-pixel, in accordance with the gate line that has been supplied with the gate signal, and
wherein the first memory is one of the memories of the sub-pixel, and the second memory is different from the first memory.