Electronic device for recovering from buffer overrun in a bus system
An electronic device includes a memory, plural master circuits, a transmission path, a detection unit, and a reset control unit. The plural master circuits read and write data from and into the memory. Plural instructions and data are transmitted through the transmission path while buffering and arbitrating the instructions and the data. The detection unit detects a buffer overrun in the transmission path. The reset control unit performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plural master circuits, affected by the buffer overrun.
1. An electronic device comprising:
a memory;
a plurality of master circuits that read and write data from and into the memory;
a plurality of monitoring devices;
a transmission path including a plurality of buses and a plurality of bus bridges through which a plurality of instructions and data are transmitted while buffering and arbitrating the instructions and the data, each of the plurality of master circuits and bus bridges including a monitoring device of the plurality of monitoring devices;
a detection unit that: (i) detects a buffer overrun in the transmission path, the detection unit including each monitoring device of the master circuits and bus bridges, and each monitoring device being configured to acquire monitoring information regarding the buffer overrun; and (ii) based on the monitoring information acquired by the monitoring device, specifies a location in the transmission path at which the buffer overrun has occurred; and
a reset control unit that performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plurality of master circuits, affected by the buffer overrun,
wherein the portion of the transmission path is at the specified location in the transmission path based on the monitoring information acquired by the monitoring device.
2. The electronic device according to claim 1 ,
wherein the detection unit determines that the buffer overrun has occurred in a case where a number of data directed from a master circuit side toward a memory side and a number of data directed from the memory side toward the master circuit side do not match each other at a specific location in the transmission path.
3. The electronic device according to claim 2 ,
wherein the detection unit determines whether or not the numbers match each other by counting the number of data directed from the master circuit side toward the memory side and the number of data directed from the memory side toward the master circuit side for each bus at least at a bus bridge provided on the transmission path.
4. The electronic device according to claim 1 ,
wherein the reset control unit resets transmission path portions and master circuits positioned on a master circuit side with respect to a location at which the buffer overrun is detected by the detection unit, and does not reset the other transmission path portions and the other master circuits.
5. The electronic device according to claim 4 ,
wherein the reset control unit resets the transmission path portions and the master circuits to be reset after stopping operation of the other transmission path portions and the other master circuits which are not to be reset.
6. An electronic device comprising:
a memory;
a plurality of master circuits that read and write data from and into the memory;
a plurality of monitoring devices;
a transmission path including a plurality of buses and a plurality of bus bridges through which a plurality of instructions and data are transmitted while buffering and arbitrating the instructions and the data, each of the plurality of master circuits and bus bridges including a monitoring device of the plurality of monitoring devices;
detection means that: (i) detects a buffer overrun in the transmission path, the detection means including each monitoring device of the master circuits and bus bridges, and each monitoring device being configured to acquire monitoring information regarding the buffer overrun; and (ii) based on the monitoring information acquired by the monitoring device, specifies a location in the transmission path at which the buffer overrun has occurred; and
reset control means that performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plurality of master circuits, affected by the buffer overrun,
wherein the portion of the transmission path is at the specified location in the transmission path based on the monitoring information acquired by the monitoring device.