Cache management using multiple cache history lists

1. A method for cache management, comprising:

receiving an I/O request associated with a processor kernel;

in response to first data that the I/O request is targeted for being missed in a cache, determining whether a first target address of the first data is recorded in one of a plurality of cache history lists;

in response to the first target address not being recorded in the plurality of cache history lists, storing, in a first node of a first free cache history list, the first target address and an initial access count of the first target address, the first free cache history list being determined in association with the processor kernel in advance;

adding the first node to a first cache history list associated with the I/O request of the plurality of cache history lists;

in response to the first target address being recorded in a second cache history list of the plurality of cache history lists, incrementing an access count stored in a second node associated with the first target address of the second cache history list; and

moving the second node to a head of the second cache history list.

2. The method according to claim 1 , further comprising:

determining whether a length of the first free cache history list is less than a predetermined threshold length; and

in response to the length being less than the predetermined threshold length, moving a tail node of the first cache history list to the first free cache history list.

3. The method according to claim 1 , further comprising:

determining whether the access count reaches a predetermined threshold count; and

in response to the access count reaching the predetermined threshold count, writing the first data in the first target address recorded in the second node into the cache.

4. The method according to claim 3 , further comprising:

in response to writing the first data into the cache, releasing the second node from the second cache history list.

5. The method according to claim 4 , the releasing comprising:

determining whether a length of a second free cache history list associated with the second node reaches a predetermined threshold length; and

in response to the length reaching the predetermined threshold length, moving the second node to the tail of the second cache history list.

6. The method according to claim 5 , further comprising:

in response to the length being less than the predetermined threshold length, moving the second node to the second free cache history list.

7. A cache manager, comprising:

at least one processing unit;

at least one memory coupled to the at least one processing unit and storing instructions executed by the at least one processing unit, the instructions, when executed by the at least one processing unit, causing the device to implement acts, including:

receiving an I/O request associated with a processor kernel;

in response to data that the I/O request is targeted for being missed in a cache, determining whether a first target address of the data is recorded in one of a plurality of cache history lists;

in response to the first target address not being recorded in the plurality of cache history lists, storing, in a first node of a first free cache history list, the first target address and an initial access count of the first target address, the first free cache history list being determined in association with the processor kernel in advance;

adding the first node to a first cache history list associated with the I/O request of the plurality of cache history lists;

in response to the first target address being recorded in a second cache history list of the plurality of cache history lists, incrementing an access count stored in a second node associated with the first target address in the second cache history list; and

moving the second node to a head of the second cache history list.

8. The cache manager according to claim 7 , the acts further comprising:

determining whether a length of the first free cache history list is less than a predetermined threshold length; and

in response to the length being less than the predetermined threshold length, moving a tail node of the first cache history list to the first free cache history list.

9. The cache manager according to claim 7 , the acts further comprising:

determining whether the access count reaches a predetermined threshold count; and

in response to the access count reaching the predetermined threshold count, writing data in the first target address recorded in the second node into the cache.

10. The cache manager according to claim 9 , the acts further comprising:

in response to finishing writing the data in the first target address into the cache, releasing the second node from the second cache history list.

11. The cache manager according to claim 10 , the acts further comprising:

determining whether a length of a second free cache history list associated with the second node reaches a predetermined threshold length;

in response to the length reaching the predetermined threshold length, moving the second node to the tail of the second cache history list.

12. The cache manager according to claim 11 , the acts further comprising:

in response to the length being less than the predetermined threshold length, moving the second node to the second free cache history list.

13. A computer program product for cache management, the computer program product comprising:

a non-transitory computer readable medium encoded with computer-executable code, the code configured to enable the execution of:

receiving an I/O request associated with a processor kernel;

in response to first data that the I/O request is targeted for being missed in a cache, determining whether a first target address of the first data is recorded in one of a plurality of cache history lists;

in response to the first target address not being recorded in the plurality of cache history lists, storing, in a first node of a first free cache history list, the first target address and an initial access count of the first target address, the first free cache history list being determined in association with the processor kernel in advance;

adding the first node to a first cache history list associated with the I/O request of the plurality of cache history lists;

in response to the first target address being recorded in a second cache history list of the plurality of cache history lists, incrementing an access count stored in a second node associated with the first target address of the second cache history list; and

moving the second node to a head of the second cache history list.

14. The computer program product of claim 13 , wherein the code is further configured to enable the execution of:

determining whether a length of the first free cache history list is less than a predetermined threshold length; and

in response to the length being less than the predetermined threshold length, moving a tail node of the first cache history list to the first free cache history list.

15. The computer program product of claim 13 , wherein the code is further configured to enable the execution of:

determining whether the access count reaches a predetermined threshold count; and

in response to the access count reaching the predetermined threshold count, writing the first data in the first target address recorded in the second node into the cache.

16. The computer program product of claim 15 , wherein the code is further configured to enable the execution of:

in response to writing the first data into the cache, releasing the second node from the second cache history list.

17. The computer program product of claim 16 , the releasing comprising:

determining whether a length of a second free cache history list associated with the second node reaches a predetermined threshold length; and

in response to the length reaching the predetermined threshold length, moving the second node to the tail of the second cache history list.