IP Library Granted Patent US 10,860,480
Granted Patent B2
US 10,860,480 · App. 16/021,719 · Granted Dec 8, 2020

Method and device for cache management

Inventors: Lifeng Yang (Beijing, CN); Ruiyong Jia (Beijing, CN); Liam Xiongcheng Li (Beijing, CN); Hongpo Gao (Beijing, CN); Xinlei Xu (Beijing, CN)
Assignee: EMC IP Holding Company LLC
G06F12/0802G06F12/0804G06F12/0846G06F12/0879G06F12/0284G06F12/126G06F2212/1024G06F2212/60
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,860,480
App. No.
16/021,719
Granted
Dec 8, 2020
Kind
B2
Abstract

Embodiments of the present disclosure relate to a method and a device for cache management. The method includes: in response to receiving a write request for a cache logic unit, determining whether a first cache space of a plurality of cache spaces associated with the cache logic unit is locked; in response to the first cache space being locked, obtaining a second cache space from the plurality of cache spaces, the second cache space being different from the first cache space and being in an unlocked state; and performing, in the second cache space, the write request for the cache logic unit.

Claims (43)

1. A method for cache management, comprising:

in response to receiving a write request for a cache logic unit, determining whether a first cache space of a plurality of cache spaces associated with the cache logic unit is locked;

in response to the first cache space not being locked, performing the write request for the cache logic unit in the first cache space;

in response to the first cache space being locked, (1) obtaining a second cache space from the plurality of cache spaces, the second cache space being different from the first cache space and being in an unlocked state; and (2) performing, in the second cache space, the write request for the cache logic unit; and

in response to subsequently receiving a read request for the cache logic unit, determining whether a target space for the read request is within the second cache space, and (1) in response to the target space being within the second cache space, returning data written by the write request into the second cache space as a response to the read request, and (2) in response to at least a part of the target space being outside the second cache space, merging data of the first and second cache spaces and returning the merged data as a response to the read request.

2. The method according to claim 1 , wherein obtaining the second cache space comprises:

recording an identifier of the write request and an address of the second cache space.

3. The method according to claim 2 , wherein the identifier of the write request indicates a time stamp upon receiving the write request.

4. The method according to claim 1 , further comprising:

in response to receiving a cache flush request, merging data in the plurality of cache spaces associated with the cache logic unit; and

writing the merged data into a backend storage address space associated with the cache logic unit.

5. The method according to claim 4 , further comprising:

after completion of writing the merged data into the backend storage address space associated with the cache logic unit, releasing records of the identifier of the write request and an address of the second cache space.

6. The method according to claim 1 , wherein each of the plurality of cache spaces comprises a plurality of cache pages, and the merging comprises:

for respective cache pages of the plurality of cache spaces, determining valid data which is last written into as the merged data.

7. A device for cache management, comprising:

at least one processing unit; and

at least one memory coupled to the at least one processing unit and storing instructions executed by the at least one processing unit, the instructions when executed by the at least one processing unit causing the device to execute acts, the acts comprising:

in response to receiving a write request for a cache logic unit, determining whether a first cache space of a plurality of cache spaces associated with the cache logic unit is locked;

in response to the first cache space not being locked, performing the write request for the cache logic unit in the first cache space;

in response to the first cache space being locked, (1) obtaining a second cache space from the plurality of cache spaces, the second cache space being different from the first cache space and being in an unlocked state; and (2) performing, in the second cache space, the write request for the cache logic unit; and

in response to subsequently receiving a read request for the cache logic unit, determining whether a target space for the read request is within the second cache space, and (1) in response to the target space being within the second cache space, returning data written by the write request into the second cache space as a response to the read request, and (2) in response to at least a part of the target space being outside the second cache space, merging data of the first and second cache spaces and returning the merged data as a response to the read request.

8. The device according to claim 7 , wherein obtaining the second cache space comprises:

recording an identifier of the write request and an address of the second cache space.

9. The device according to claim 8 , wherein the identifier of the write request indicates a time stamp upon receiving the write request.

10. The device according to claim 7 , the acts further comprising:

in response to receiving a cache flush request, merging data in the plurality of cache spaces associated with the cache logic unit; and

writing the merged data into a backend storage address space associated with the cache logic unit.

11. The device according to claim 10 , the acts further comprising:

after completion of writing the merged data into the backend storage address space associated with the cache logic unit, releasing a record of the identifier of the write request and an address of the second cache space.

12. The device according to claim 7 , wherein each of the plurality of cache spaces comprises a plurality of cache pages, and the merging comprises:

for respective cache pages of the plurality of cache spaces, determining valid data which is last written into as the merged data.

13. A computer program product for cache management, the computer program product comprising:

a non-transitory computer readable medium encoded with computer executable code, wherein the code is configured for the execution of:

in response to receiving a write request for a cache logic unit, determining whether a first cache space of a plurality of cache spaces associated with the cache logic unit is locked;

in response to the first cache space not being locked, performing the write request for the cache logic unit in the first cache space;

in response to the first cache space being locked, (1) obtaining a second cache space from the plurality of cache spaces, the second cache space being different from the first cache space and being in an unlocked state; and (2) performing, in the second cache space, the write request for the cache logic unit; and

in response to subsequently receiving a read request for the cache logic unit, determining whether a target space for the read request is within the second cache space, and (1) in response to the target space being within the second cache space, returning data written by the write request into the second cache space as a response to the read request, and (2) in response to at least a part of the target space being outside the second cache space, merging data of the first and second cache spaces and returning the merged data as a response to the read request.

14. The computer program product according to claim 13 , wherein obtaining the second cache space comprises:

recording an identifier of the write request and an address of the second cache space.

15. The method according to claim 1 , wherein the merging data of the first and second cache spaces includes:

for first data residing in the second cache space, selecting that first data from the second cache space as a first part of the merged data returned in response to the read request; and

for second data residing in the first cache space and not residing in the second cache space, selecting that second data from the first cache space as a second part of the merged data returned in response to the read request.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (047648/0422) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060160/0862 →
RELEASE OF SECURITY INTEREST AT REEL 047648 FRAME 0346 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058298/0510 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Oct 12, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 047648/0422 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Oct 12, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 047648/0346 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2018
From: YANG, LIFENG; LI, LIAM XIONGCHENG; JIA, RUIYONG; GAO, HONGPO; XU, XINLEI
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 046573/0591 →