IP Library Granted Patent US 10,481,817
Granted Patent B2
US 10,481,817 · App. 16/022,339 · Granted Nov 19, 2019

Methods and apparatus to optimize dynamic memory assignments in multi-tiered memory systems

Inventors: Kshitij Doshi (Tempe, AZ); Andreas Kleen (Portland, OR); Harshad Sane (Portland, OR)
Assignee: INTEL CORPORATION
G06F3/0631G06F3/0604G06F3/0653G06F3/0656G06F3/0683G06F9/5016
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Quick Facts
Patent No.
US 10,481,817
App. No.
16/022,339
Granted
Nov 19, 2019
Kind
B2
Abstract

Methods, apparatus, systems and articles of manufacture to optimize dynamic memory assignments in multi-tiered memory systems are disclosed. An example computer readable storage medium comprises instructions to, during an offline profiling run of a computer application: responsive to a first malloc function call, perform a first backtrace to identify a first path preceding the first malloc function call and identify a size of a buffer in memory allocated to the first path; and determine an indicator corresponding to a temperature of the buffer allocated to the first path; and during runtime: responsive to a second malloc function call, perform a second backtrace to identify a second path preceding the second malloc function call; and responsive to the second path corresponding to the first path, allocate memory from a tier of memory based on the indicator.

Claims (59)

1. A non-transitory computer readable storage medium comprising executable computer program instructions which, when executed, cause a machine to at least:

during an offline profiling run of a computer application:

responsive to a first malloc function call, perform a first backtrace to identify a first path preceding the first malloc function call and identify a size of a buffer in memory allocated to the first path; and

determine an indicator corresponding to a temperature of the buffer allocated to the first path; and

during runtime:

responsive to a second malloc function call, perform a second backtrace to identify a second path preceding the second malloc function call; and

responsive to the second path corresponding to the first path, allocate memory from a tier of memory based on the indicator.

2. The computer readable storage medium of claim 1 , wherein:

responsive to the indicator corresponding to a first temperature, the tier of memory is a first tier corresponding to at least one of a first latency and a first bandwidth; and

responsive to the indicator corresponding to a second temperature lower than the first temperature, the tier of memory is a second tier corresponding to at least one of a second latency higher than the first latency and a second bandwidth lower than the first bandwidth.

3. The computer readable storage medium of claim 2 , wherein the instructions cause the machine to, responsive to the indicator corresponding to the second temperature and the first tier has capacity to allocate memory, allocate memory from the first tier of memory.

4. The computer readable storage medium of claim 1 , wherein the instructions cause the machine to:

store a correspondence between the first path and the temperature in a database during the offline profiling run; and

determine that the second path corresponds to the first path by comparing the second path with the first path.

5. The computer readable storage medium of claim 1 , wherein the instructions cause the machine to, during the offline profiling mode:

assign a buffer tag to the buffer;

compute a path temperature for the first path relative to other paths corresponding to other malloc function calls determined during the offline profiling run based on the buffer tag;

determine a set of markers corresponding to the other paths;

trace the set of markers to that belong on the first path;

assign a path signature to the first path based on the traced set of markers; and

store the path signature with the path temperature in a database.

6. The computer readable storage medium of claim 1 , wherein the instructions cause the machine to, during the offline profiling run, filter out at least one of malloced paths that correspond to a low temperature or malloced paths that correspond to high capacity allocations.

7. The computer readable storage medium of claim 1 , wherein the instructions cause the machine to, responsive to the tier of memory being unavailable, rebalance the memory across tiers of the memory.

8. The computer readable storage medium of claim 1 , wherein the indicator corresponding to the temperature corresponds to a frequency that the buffer allocated to the first path will be accessed by the computer application.

9. An apparatus to perform dynamic memory assignments in multi-tiered memory systems, the apparatus comprising:

a malloc information processor to, during an offline profiling run of a computer application, perform a first backtrace responsive to a first malloc function call to identify a first path preceding the first malloc function call and identify a size of a buffer in memory allocated to the first path;

a temperature determiner to determine an indicator corresponding to a temperature of the buffer allocated to the first path;

a path determiner to, during runtime, perform a second backtrace responsive to a second malloc function call to identify a second path preceding the second malloc function call; and

a memory tier allocator to, responsive to the second path corresponding to the first path, allocate memory from a tier of memory based on the indicator.

10. The apparatus of claim 9 , wherein:

responsive to the indicator corresponding to a first temperature, the tier of memory is a first tier corresponding to at least one of a first latency and a first bandwidth; and

responsive to the indicator corresponding to a second temperature lower than the first temperature, the tier of memory is a second tier corresponding to at least one of a second latency higher than the first latency and a second bandwidth lower than the first bandwidth.

11. The apparatus of claim 10 , wherein the memory tier allocator is to, responsive to the indicator corresponding to the second temperature and the first tier has capacity to allocate memory, allocate memory from the first tier of memory.

12. The apparatus of claim 9 , further including a database to store a correspondence between the first path and the temperature during the offline profiling run, the memory tier allocator to determine that the second path corresponds to the first path by comparing the second path with the first path.

13. The apparatus of claim 9 , further including:

a path processor to, during the offline profiling mode, assign a buffer tag to the buffer;

the temperature determiner to compute a path temperature for the first path relative to other paths corresponding to other malloc function calls determined during the offline profiling run based on the buffer tag;

the path processor to:

determine a set of markers corresponding to the other paths;

trace the set of markers to that belong on the first path; and

assign a path signature to the first path based on the traced set of markers; and

a database to store the path signature with the path temperature.

14. The apparatus of claim 9 , further including a path processor to, during the offline profiling run, filter out at least one of malloced paths that correspond to a low temperature or malloced paths that correspond to high capacity allocations.

15. The apparatus of claim 9 , further including a memory balancer to, responsive to the tier of memory being unavailable, rebalance the memory across tiers of the memory.

16. The apparatus of claim 9 , wherein the indicator corresponding to the temperature corresponds to a frequency that the buffer allocated to the first path will be accessed by the computer application.

17. A method to perform dynamic memory assignments in multi-tiered memory systems, the method comprising:

during an offline profiling run of a computer application:

responsive to a first malloc call function, performing a first backtrace to identify a first path preceding the first malloc function call and identify a size of a buffer in memory allocated to the first path; and

determining an indicator corresponding to a temperature of the buffer allocated to the first path; and

during runtime:

responsive to a second malloc function call, performing a second backtrace to identify a second path preceding the second malloc function call; and

responsive to the second path corresponding to the first path, allocating memory from a tier of memory based on the indicator.

18. The method of claim 17 , wherein:

responsive to the indicator corresponding to a first temperature, the tier of memory is a first tier corresponding to at least one of a first latency and a first bandwidth; and

responsive to the indicator corresponding to a second temperature lower than the first temperature, the tier of memory is a second tier corresponding to at least one of a second latency higher than the first latency and a second bandwidth lower than the first bandwidth.

19. The method of claim 18 , further including, responsive to the indicator corresponding to the second temperature and the first tier has capacity to allocate memory, allocating memory from the first tier of memory.

20. The method of claim 17 , further including:

storing a correspondence between the first path and the temperature in a database during the offline profiling run; and

determining that the second path corresponds to the first path by comparing the second path with the first path.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2018
From: DOSHI, KSHITIJ; KLEEN, ANDREAS; SANE, HARSHAD
To: INTEL CORPORATION
Reel/Frame 046404/0777 →
Continuity (1)
Related Publication 20190042124A1 · Feb 7, 2019
Cited By (2)
US 12,379,869 US 12,462,149