IP Library Granted Patent US 10,672,909
Granted Patent B2
US 10,672,909 · App. 16/022,686 · Granted Jun 2, 2020

Strained gate semiconductor device having an interlayer dielectric doped with oxygen and a large species material

Inventors: Cheng-Ta Wu (Chiayi County, TW); Chii-Ming Wu (Taipei, TW); Shiu-Ko Jangjian (Tainan, TW); Kun-Tzu Lin (Tainan, TW); Lan-Fang Chang (Yunlin County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L29/7856H01L21/02321H01L21/02323H01L21/28158H01L21/3115H01L21/31155H01L21/823821H01L27/0924H01L29/401H01L29/42364H01L29/512H01L29/66795H01L29/7843H01L29/7851H01L29/495H01L29/513
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Quick Facts
Patent No.
US 10,672,909
App. No.
16/022,686
Granted
Jun 2, 2020
Kind
B2
Abstract

A semiconductor device including a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a first portion doped with an oxygen-containing material, a second portion doped with a large species material, and a third portion being undoped by the oxygen-containing material and the large species material.

Claims (37)

1. A semiconductor device, comprising:

a gate stack over a substrate; and

an interlayer dielectric (ILD) at least partially enclosing the gate stack, wherein the ILD comprises:

a first portion doped with an oxygen-containing material,

a second portion doped with a large species material, and

a third portion being undoped by the oxygen-containing material and the large species material.

2. The semiconductor device of claim 1 , wherein the second portion has a first lattice constant and the third portion has a second lattice constant, and the second lattice constant is smaller than the first lattice constant.

3. The semiconductor device of claim 1 , wherein the large species material is selected from a noble gas, a semiconductor material, or a metal.

4. A semiconductor device, comprising:

a gate stack over a fin material;

an interlayer dielectric (ILD) over the fin material and at least partially enclosing the gate stack, wherein the ILD comprises:

a first portion adjacent to a top surface of the ILD, the first portion being doped with an oxygen-containing species and a large species material, and

a second portion, wherein the second portion is doped with the large species material, and the large species material includes a metal selected from the group consisting of tin, gallium, and indium.

5. The semiconductor device of claim 4 , wherein the ILD further comprises a third portion beneath the second portion, and the third portion is an undoped portion of the ILD.

6. The semiconductor device of claim 4 , wherein the second portion is doped with a plurality of large species materials.

7. The device of claim 4 , wherein the large species material includes a noble gas selected from the group consisting of argon, krypton, and xenon.

8. The device of claim 4 , wherein the large species material includes a semiconductor material selected from the group consisting of silicon, germanium, phosphorous, and arsenic.

9. The device of claim 4 , wherein the second portion is free of the oxygen-containing species.

10. A semiconductor device, comprising:

a gate stack over a substrate; and

an interlayer dielectric (ILD) at least partially enclosing the gate stack, wherein the ILD comprises:

a first portion having a first sidewall,

a second portion over the first portion, wherein the second portion comprises an oxygen-containing material and a large species material, and the second portion has a second sidewall angled with respect to the first sidewall, and

a third portion between the first portion and the second portion, wherein the third portion comprises the large species material, wherein the third portion comprises a third sidewall parallel to the second sidewall.

11. The semiconductor device of claim 10 , wherein an angle between the first sidewall and the second sidewall is a positive angle.

12. The semiconductor device of claim 10 , wherein an angle between the first sidewall and the second sidewall is a positive angle of at most 8-degrees.

13. The semiconductor device of claim 10 , wherein the second sidewall is angled at a clockwise obtuse angle with respect to the first sidewall.

14. The semiconductor device of claim 13 , wherein the third portion is free of the oxygen-containing material.

15. The semiconductor device of claim 13 , wherein the third portion comprises a fourth sidewall parallel to the first sidewall.

16. The semiconductor device of claim 13 , wherein the first portion is free of the oxygen-containing material and the large species material.

17. The semiconductor device of claim 13 , wherein the fourth sidewall is between the third sidewall and the first sidewall.

18. The semiconductor device of claim 10 , wherein the large species material comprises at least one of argon, krypton, xenon, silicon, germanium, phosphorous, arsenic, tin, gallium, or indium.

19. The semiconductor device of claim 10 , further comprising raised source/drain regions.

20. The semiconductor device of claim 10 , wherein the gate stack comprises:

a gate oxide;

a work function layer; and

a conductive layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2018
From: WU, CHENG-TA; WU, CHII-MING; JANGJIAN, SHIU-KO; LIN, KUN-TZU; CHANG, LAN-FANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 046234/0687 →
Continuity (3)
Division 15399241 · Jan 5, 2017
Provisional Application 62427556 · Nov 29, 2016
Related Publication 20180308979A1 · Oct 25, 2018