Stress relieving semiconductor layer
A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
1. A structure comprising:
a substrate;
a nucleation layer located on the substrate, wherein the nucleation layer is formed of a plurality of nucleation islands; and
a cavity containing layer located over the nucleation layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
2. The structure of claim 1 , where in the cavity containing layer has a thickness between approximately one micron and approximately ten microns.
3. The structure of claim 1 , wherein the characteristic size of the plurality of cavities is in a range of approximately ten nanometers to approximately four thousand nanometers.
4. The structure of claim 1 , further comprising a semiconductor layer immediately adjacent to the cavity containing layer, wherein the semiconductor layer contains no large scale cavities.
5. The structure of claim 4 , wherein the semiconductor layer comprises Al x Ga 1-x N, wherein 0<x<1.
6. The structure of claim 5 , wherein x>0.8.
7. The structure of claim 1 , wherein a surface of the substrate adjacent to the nucleation layer is inclined at an angle.
8. The structure of claim 7 , wherein the angle is equal to or greater than 0.6 degrees and equal to or less than 3 degrees.
9. The structure of claim 1 , further comprising a second nucleation layer located directly on the nucleation layer including the plurality of nucleation islands, wherein the nucleation layer including the plurality of nucleation islands is partially-etched.
10. The structure of claim 1 , wherein the substrate is nano-patterned.
11. A device comprising:
a substrate;
a nucleation layer located on the substrate, wherein the nucleation layer is formed of a plurality of nucleation islands;
a cavity containing layer located over the nucleation layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers; and
a semiconductor layer located over the cavity containing layer, wherein the semiconductor layer contains no cavities.
12. The device of claim 11 , where in the cavity containing layer has a thickness between approximately one micron and approximately ten microns.
13. The device of claim 11 , wherein the characteristic size of the plurality of cavities is in a range of approximately ten nanometers to approximately four thousand nanometers.
14. The device of claim 11 , wherein the semiconductor layer comprises Al x Ga 1-x N, wherein 0<x<1.
15. The device of claim 14 , wherein x>0.8.
16. The device of claim 11 , wherein a surface of the substrate adjacent to the nucleation layer is inclined at an angle equal to or greater than 0.6 degrees and equal to or less than 3 degrees.
17. The device of claim 11 , further comprising a second nucleation layer located directly on the nucleation layer including the plurality of nucleation islands, wherein the nucleation layer including the plurality of nucleation islands is partially-etched.
18. The device of claim 11 , wherein the substrate is nano-patterned.
19. A method comprising:
fabricating a semiconductor structure, wherein the fabricating includes:
growing a nucleation layer on a substrate, wherein the nucleation layer is formed of a plurality of nucleation islands;
forming a cavity containing layer over the nucleation layer, wherein the cavity containing layer has a thickness greater than two monolayers and a plurality of cavities; and
forming a semiconductor layer directly on the cavity containing layer, wherein the semiconductor layer comprises Al x Ga 1-x N, wherein 0.8<x<1.
20. The method of claim 19 , wherein the fabricating further comprises:
partially etching the nucleation layer and the substrate at a temperature of at least 1000 degrees Celsius in an H 2 ambient, such that the substrate is nano-patterned; and
growing a second nucleation layer directly on the partially etched nucleation layer and the nano-patterned substrate.