IP Library Granted Patent US 10,629,717
Granted Patent B2
US 10,629,717 · App. 16/023,822 · Granted Apr 21, 2020

High power device

Inventor: Kenichi Sugita (Kawasaki, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Infrastructure Systems & Solutions Corporation
H01L29/7783H01L29/15H01L29/155H01L29/205H01L29/2003
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Quick Facts
Patent No.
US 10,629,717
App. No.
16/023,822
Granted
Apr 21, 2020
Kind
B2
Abstract

A high power device including with a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, and a third nitride semiconductor layer containing an Al element formed on the second nitride semiconductor layer. The second nitride semiconductor layer is a multiple quantum well layer in which a nitride semiconductor layer containing an In element and a nitride semiconductor layer not containing an In element are alternately stacked.

Claims (25)

1. A high power device comprising:

a first nitride semiconductor layer;

a second nitride semiconductor layer formed on the first nitride semiconductor layer, wherein the second nitride semiconductor layer is a multiple quantum well layer in which an InN layer and a GaN layer are alternately stacked;

a third nitride semiconductor layer containing an Al element formed on the second nitride semiconductor layer; and

a source electrode, a gate electrode and a drain electrode formed on the third nitride semiconductor layer, wherein the source electrode, the gate electrode and the drain electrode are formed separately to each other, and the source electrode and the drain electrode are formed so as to sandwich the gate electrode.

2. The high power device according to claim 1 , wherein:

a film thickness of the InN layer is not more than 10 nm, and

a film thickness of the GaN layer is not more than 20 nm.

3. The high power device according to claim 2 , wherein:

a number of pairs of the InN layer and the GaN layer in the multiple quantum layer is not more than 100.

4. The high power device according to claim 1 , wherein:

the third nitride semiconductor layer is an AlyGal-yN layer (1≥y>0).

5. The high power device according to claim 1 , further comprising a substrate and a buffer layer provided on the substrate;

wherein the first nitride semiconductor layer is formed on the buffer layer, and

wherein the buffer layer is an InaAlbGa(1-a-b)N layer (1≥a≥0, 1≥b≥0).

6. The high power device according to claim 4 , further comprising a substrate and a buffer layer provided on the substrate;

wherein the first nitride semiconductor layer is formed on the buffer layer, and

wherein the buffer layer is an InaAlbGa(1-a-b)N layer (1≥a≥0, 1≥b≥0).

7. The high power device according to claim 5 , wherein:

the substrate is any one of Si, SiC, α—Al 2 O 3 , ZnO, GaN, AlN and diamond.

8. The high power device according to claim 6 , wherein:

the substrate is any one of Si, SiC, α—Al 2 O 3 , ZnO, GaN, AlN and diamond.

9. The high power device according to claim 1 , wherein:

a film thickness of the InN layer is 0.26 nm, and

a film thickness of the GaN layer is not more than 20 nm.

Assignments (2)
MERGER Recorded Jul 29, 2025
From: TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 072239/0263 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2018
From: SUGITA, KENICHI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION
Reel/Frame 046241/0617 →
Priority Claims (1)
JP 2017-188175 · Sep 28, 2017 · national
Continuity (1)
Related Publication 20190097033A1 · Mar 28, 2019