Tiled electrochromic devices on carrier glass and methods of making the same
A tiled electrochromic (EC) device comprises a carrier glass, a first EC panel laminated to the carrier glass, a second EC panel laminated to the carrier glass, and a seam between the first EC panel and second EC panel. The first and second EC panels comprise an active area, a clear state and a dark state, and the tiled EC device is capable of switching between a clear state and a dark state.
1. A tiled electrochromic (EC) device, comprising:
a carrier glass;
a first EC device laminated to the carrier glass comprising a first active area, a first clear state and a first dark state;
a second EC device laminated to the carrier glass comprising a second active area, a second clear state and a second dark state;
a third active area comprising the first active area and second active areas; and
a seam between the first and second EC devices;
wherein:
the carrier glass has an area greater than 2 m 2 ;
the first and second clear states comprise a CIE-Lab L* in transmission from 70 to 95, b* in transmission from −8 to 8, and a* in transmission from −4 to 4;
the third active area comprises a third clear state, a third dark state, and a plurality of tint states between the third clear state and the third dark state, wherein the plurality of tint states are along a continuum of tints comprising a Tvis from 0.1% to 80%; and
a deltaE between any two points within the third active area of the tiled EC device in transmission is less than 10 in the third clear state, the third dark state, and at all tint states in the plurality of tint states, across the large area tiled EC device in all lateral dimensions.
2. The tiled EC device of claim 1 , wherein the first and second clear states further comprise a Tvis from 70% to 80%.
3. The tiled EC device of claim 1 , wherein the first and second dark states comprise a CIE-Lab L* in transmission from 0 to 30, b* in transmission from −5 to −2, a* in transmission from −7 to −5, and a Tvis from 0.01% to 5%.
4. The tiled EC device of claim 1 , wherein the seam comprises a seam region, wherein a deltaE between any point within the seam region and any point within the first or second active areas is less than 10, when the first or second EC devices are in the first or second clear state, respectively, or the first or second dark state, respectively.
5. The tiled EC device of claim 1 , further comprising a covering obscuring the seam, wherein the deltaE between any point within the covering and any point within the first or second active areas is less than 10, when the first or second EC devices are in the first or second dark state, respectively.
6. The tiled EC device of claim 1 , wherein a width of the seam is less than 0.05 cm.
7. The tiled EC device of claim 1 , further comprising:
a first set of bus bars in the first EC device; and
a second set of bus bars in the second EC device, wherein
the first and second set of bus bars are aligned with one another across the seam, and at least one of the bus bars in the first and second EC devices is located at a peripheral edge of the tiled EC device.
8. The tiled EC device of claim 1 , further comprising:
a first sequestration terminal in the first EC device;
a second sequestration terminal in the second EC device;
a first sense voltage terminal in the first EC device; and
a second sense voltage terminal in the second EC device.
9. The tiled EC device of claim 8 , further comprising:
a first set of bus bars in the first EC device;
a second set of bus bars in the second EC device; and
an electrical connection between the first and second EC devices comprising one or more circuit boards connecting the first and second sets of bus bars, first and second sense voltage terminals, and first and second sequestration terminals between the first EC device and the second EC device.
10. The tiled EC device of claim 9 , further comprising:
an upper and a lower substrate in the first EC device;
an upper and a lower substrate in the second EC device;
the upper substrate in the first EC device is offset in a lateral direction from the lower substrate in the first EC device along at least a portion of an edge of the first EC device; and
the first bus bars, first sense voltage terminals and first sequestration terminals that are on the lower substrate of the first EC device are exposed by the upper substrate of the first EC device being offset in the lateral direction from the lower substrate of the first EC device.
11. The tiled EC device of claim 1 , further comprising:
one or more first gradient electrically conductive layers in the first EC device; and
one or more second gradient electrically conductive layers in the second EC device, wherein
the gradient direction of the one or more first gradient electrically conductive layers in the first EC device is parallel to the gradient direction of the second gradient transparent conductor layers in the second EC device.
12. The tiled EC device of claim 11 , further comprising:
a first visually perceptible pattern in the first EC device; and
a second visually perceptible pattern in the second EC device, wherein
the first and second visually perceptible patterns in the first and second EC devices respectively, are aligned with one another across the seam between the first and second EC devices.
13. A tiled electrochromic (EC) device, comprising:
a carrier glass;
a first EC device laminated to the carrier glass comprising a first active area, a first clear state and a first dark state;
a second EC device laminated to the carrier glass comprising a second active area, a second clear state and a second dark state; and
a seam between the first and second EC devices;
wherein:
the carrier glass has an area greater than 2 m 2 ;
the first and second clear states comprise a CIE-Lab L* in transmission from 70 to 95, b* in transmission from −8 to 8, and a* in transmission from −4 to 4; and
the seam comprises a seam region, wherein a deltaE between any point within the seam region and any point within the first or second active areas is less than 10, when the first or second EC devices are in the first or second clear state, respectively, or the first or second dark state, respectively.
14. The tiled EC device of claim 13 , wherein the first and second clear states further comprise a Tvis from 70% to 80%.
15. The tiled EC device of claim 13 , wherein the first and second dark states comprise a CIE-Lab L* in transmission from 0 to 30, b* in transmission from −5 to −2, a* in transmission from −7 to −5, and a Tvis from 0.01% to 5%.
16. The tiled EC device of claim 13 , wherein a width of the seam is less than 0.05 cm.
17. The tiled EC device of claim 13 , further comprising:
a first set of bus bars in the first EC device; and
a second set of bus bars in the second EC device, wherein
the first and second set of bus bars are aligned with one another across the seam, and at least one of the bus bars in the first and second EC devices is located at a peripheral edge of the tiled EC device.
18. The tiled EC device of claim 13 , further comprising:
one or more first gradient electrically conductive layers in the first EC device; and
one or more second gradient electrically conductive layers in the second EC device, wherein
the gradient direction of the one or more first gradient electrically conductive layers in the first EC device is parallel to the gradient direction of the second gradient transparent conductor layers in the second EC device.
19. The tiled EC device of claim 18 , further comprising:
a first visually perceptible pattern in the first EC device; and
a second visually perceptible pattern in the second EC device, wherein
the first and second visually perceptible patterns in the first and second EC devices, respectively, are aligned with one another across the seam between the first and second EC devices.