IP Library Granted Patent US 10,546,826
Granted Patent B2
US 10,546,826 · App. 16/025,575 · Granted Jan 28, 2020

Device containing and method of providing carbon covered copper layer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,546,826
App. No.
16/025,575
Granted
Jan 28, 2020
Kind
B2
Abstract

A device and method of preventing corrosion of a copper layer in a PCB is disclosed. A first dielectric is disposed on a substrate. A copper layer is plated in an opening in the first dielectric and, after conditioning the copper layer, a redistribution layer is plated on the copper layer. A solder resist layer is disposed above the copper layer. A solder ball is disposed in an opening in the solder resist layer. The solder ball is in conductive contact with the copper layer and in physical contact with the redistribution layer. A non-conductive carbon layer is disposed on and in contact with the redistribution layer or tsi-diehe solder resist layer. The carbon layer is substantially thinner than the copper layer and acts as a diffusion barrier to moisture for the copper layer.

Claims (44)

1. A device comprising:

a substrate comprising at least one of a semiconductor or mold compound;

a first dielectric disposed on substrate;

a copper layer plated in an opening in the first dielectric;

a solder resist layer above the copper layer;

a solder ball in an opening in the solder resist layer, the solder ball in conductive contact with the copper layer; and

a non-conductive carbon layer on the substrate, the non-conductive carbon layer formed from carbon rather than a carbon compound and configured to act as a diffusion barrier to moisture for the copper layer.

2. The device of claim 1 , wherein the carbon layer is disposed on the substrate below the first dielectric.

3. The device of claim 1 , wherein the carbon layer is disposed between the solder resist layer and the first dielectric.

4. The device of claim 1 , wherein the carbon layer is disposed on the solder resist layer.

5. The device of claim 4 , wherein the carbon layer is further disposed on at least one of the solder ball or an interconnect element.

6. The device of claim 4 , wherein the carbon layer is adjacent to the solder ball and the solder ball is free from the carbon layer.

7. The device of claim 1 , further comprising:

a redistribution layer disposed on and in electrical contact with the copper layer,

wherein the solder ball is in physical contact with the redistribution layer and does not overlie the copper layer, and the carbon layer is disposed between the solder resist layer and the redistribution layer and is not disposed between the solder ball and the redistribution layer.

8. The device of claim 1 , further comprising a second non-conductive carbon layer on the substrate configured to act as another diffusion barrier to moisture for the copper layer, the second non-conductive carbon layer disposed on a same side of the copper layer as the non-conductive carbon layer, the non-conductive carbon layer and second non-conductive carbon layer separated by at least one dielectric.

9. The device of claim 1 , further comprising a second non-conductive carbon layer on the substrate configured to act as another diffusion barrier to moisture for the copper layer, the second non-conductive carbon layer disposed on an opposite side of the copper layer as the non-conductive carbon layer, the non-conductive carbon layer and second non-conductive carbon layer separated by at least one dielectric.

10. The device of claim 1 , wherein the device is disposed in one of a Wafer Level Ball Grid Array (WLB), an Embedded Wafer Level Ball Grid Array (eWLB), Flip-Chip (FC) bonded or embedded packages.

11. A method for protecting a copper layer from, the method comprising:

spinning on a first dielectric on a substrate comprising at least one of a semiconductor or mold compound;

patterning the first dielectric to provide an opening in the first dielectric;

plating a copper layer in the opening in the first dielectric;

plating a redistribution layer on the copper layer;

spinning on and patterning the solder resist layer to provide an opening in the solder resist layer to the redistribution layer; and

attaching a solder ball in the opening in the solder resist layer, the solder ball in physical contact with the redistribution layer and in conductive contact with the copper layer,

wherein a non-conductive carbon layer that provides a diffusion barrier to moisture for the copper layer is deposited on the substrate,

the non-conductive carbon layer is formed from carbon rather than a carbon compound.

12. The method of claim 11 , wherein the carbon layer is disposed on the substrate below the first dielectric.

13. The method of claim 11 , wherein the carbon layer is disposed between the solder resist layer and the first dielectric.

14. The method of claim 11 , wherein the carbon layer is disposed on the solder resist layer.

15. The method of claim 14 , wherein the carbon layer is further disposed on at least one of the solder ball or an interconnect element.

16. The method of claim 14 , wherein the carbon layer is not disposed on the solder ball.

17. The method of claim 11 , further comprising:

depositing a second non-conductive carbon layer on the substrate, the second non-conductive carbon layer acting as another diffusion barrier to moisture for the copper layer, the second non-conductive carbon layer disposed on a same side of the copper layer as the non-conductive carbon layer, the non-conductive carbon layer and second non-conductive carbon layer separated by the solder resist layer.

18. A printed circuit board (PCB) comprising:

a substrate comprising at least one of a semiconductor or mold compound;

a first dielectric disposed on substrate;

a copper layer plated in an opening in the first dielectric;

a redistribution layer plated on the copper layer;

a solder resist layer disposed above the copper layer;

a solder ball disposed in an opening in the solder resist layer, the solder ball in conductive contact with the copper layer and in physical contact with the redistribution layer; and

a non-conductive carbon layer disposed on and in contact with one of the redistribution layer or the solder resist layer, the carbon layer configured to act as a diffusion barrier to moisture for the copper layer, the carbon layer being substantially thinner than the copper layer, the carbon layer is further disposed on the solder ball.

19. The PCB of claim 18 , further comprising a second non-conductive carbon layer configured to act as another diffusion barrier to moisture for the copper layer, the second non-conductive carbon layer disposed on the other of the redistribution layer or the solder resist layer.

20. The device of claim 4 , wherein the carbon layer is further disposed on the solder ball.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2023
From: WAGNER, THOMAS; WAIDHAS, BERND; IRSIGLER, ROLAND; WOLTER, ANDREAS
To: INTEL CORPORATION
Reel/Frame 064437/0657 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056337/0609 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2019
From: SEIDEMANN, GEORG
To: INTEL IP CORPORATION
Reel/Frame 049392/0521 →