System and method for power analysis resistant clock
A system and method to mitigate or complicate the use of differential power analysis (DPA) and simple power analysis (SPA) in the attack of a targeted integrated circuit, or device containing an integrated circuit, that is processing sensitive information. The system and method modifies the regularity of a clock that initiates the power events within the circuit such that subsequent processing of information does not always occur at the same time.
1. An apparatus resistant to power analysis comprising:
a control logic circuit configured to distribute a system clock signal in the apparatus;
a linear feedback shift register configured to output a pseudo-random bit stream;
a first decoder configured to receive the pseudo-random bit stream and to output a selector signal;
a counter configured to output a linear feedback shift register clock pattern;
a second decoder configured to receive the linear feedback shift register clock pattern, detect when the linear feedback shift register will repeat, and to output a signal to the control logic circuit; and
a multiplexer configured to receive the selector signal and the linear feedback shift register clock pattern and to output a pseudo-random clock signal, wherein the pseudo-random clock signal is used to clock a circuit that processes data.
2. The apparatus of claim 1 , wherein the data is encrypted.
3. The apparatus of claim 1 , wherein the counter comprises a plurality of flip-flops configured to achieve a maximal length.
4. The apparatus of claim 1 , wherein the control logic circuit is further configured to receive a reset signal and an error signal.
5. The apparatus of claim 4 , wherein the error signal is used to safeguard the counter against the use of a lockup state.
6. The apparatus of claim 4 , wherein the control logic circuit is further configured to ensure that a starting sequence is varied following a reset or power-on event.
7. A method for generating a power analysis-resistant clock signal, the method comprising the steps of:
outputting, by a first linear feedback shift register, a first value;
receiving the first value, by a first decoder, and outputting a first active signal;
outputting, by a second linear feedback shift register, a second value;
receiving, by a multiplexer, the first active signal and the second value, and outputting a clockout, wherein the multiplexer uses the first active signal to select the clockout from the second value;
distributing, by a control logic circuit, a system clock signal to the first linear feedback shift register and the second linear feedback shift register;
further wherein the second value is also received by a second decoder that outputs a second signal that is received by the control logic circuit to increment the first linear feedback shift register until the first linear feedback shift register wraps around.
8. The method of claim 7 , wherein an error signal identifies if the first linear feedback shift register or the second linear feedback shift register enters an illegal state.
9. The method of claim 8 , further comprising the step of stopping, re-initializing, or restarting, by the control logic circuit, using a preset signal.
10. The method of claim 9 , wherein the first linear feedback shift register or the second linear feedback shift register have a fixed value initialized.
11. The method of claim 9 , wherein the first linear feedback shift register or the second linear feedback shift register have a value initialized based on a value loaded from a prior saved value.
12. The method of claim 9 , wherein the first linear feedback shift register or the second linear feedback shift register have a value initialized from a randomly generated value that is not an illegal state.