Switches with multiple field-effect transistors having proximity electrodes

1. A field-effect transistor (FET) device comprising:

an insulator layer;

a substrate layer implemented under the insulator layer;

an active silicon layer implemented over the insulator layer with a first active FET and a second active FET formed from the active silicon layer, each of the first active FET and the second active FET including a source terminal, a drain terminal, and a gate terminal;

a first proximity electrode implemented adjacent to the first active FET, the first proximity electrode configured to receive a voltage and to generate an electric field between the first proximity electrode and a region generally underneath the first active FET; and

a second proximity electrode implemented adjacent to the second active FET, the second proximity electrode configured to receive a voltage and to generate an electric field between the second proximity electrode and a region generally underneath the second active FET.

2. The FET device of claim 1 further comprising an electrical connection implemented to provide a signal to the first proximity electrode and to the second proximity electrode to adjust an operating condition of the FET device.

3. The FET device of claim 1 further comprising a substrate contact feature implemented to provide an electrical connection to the substrate layer.

4. The FET device of claim 3 wherein the substrate contact feature is positioned to be laterally spaced from the first active FET by a distance greater than a lateral spacing of the first proximity electrode from the first active FET or to be laterally spaced from the second active FET by a distance greater than a lateral spacing of the second proximity electrode from the second active FET.

5. The FET device of claim 1 wherein the first proximity electrode is positioned to be laterally offset from a nearest edge of the first active FET by a distance that is less than 10 μm.

6. The FET device of claim 5 wherein the second proximity electrode is positioned to be laterally offset from a nearest edge of the second active FET by a distance that is less than 10 μm.

7. The FET device of claim 1 wherein the first proximity electrode or the second proximity electrode is configured to extend through the insulator layer and contact at least a portion of the substrate layer.

8. The FET device of claim 1 further comprising an interface layer implemented between the substrate layer and the insulator layer.

9. The FET device of claim 1 wherein the interface layer includes a trap-rich layer.

10. The FET device of claim 9 wherein the first proximity electrode or the second proximity electrode is configured to extend through the insulator layer but not the trap-rich layer.

11. The FET device of claim 9 wherein the first proximity electrode or the second proximity electrode is configured to extend through the insulator layer and the trap-rich layer.

12. The FET device of claim 1 wherein the substrate layer includes a plurality of doped regions having amorphous and high resistivity properties.

13. The FET device of claim 12 wherein the first proximity electrode or the second proximity electrode is configured to extend through the insulator layer but not the doped regions.

14. The FET device of claim 12 wherein the first proximity electrode or the second proximity electrode is configured to extend through the insulator layer and the doped regions.

15. The FET device of claim 1 wherein the first proximity electrode and the second proximity electrode are configured to be biased using a proximity bias signal.

16. The FET device of claim 1 wherein the first proximity electrode is configured to be biased using a first proximity bias signal and the second proximity electrode is configured to be biased using a second proximity bias signal different from the first proximity bias signal.

17. A radio-frequency (RF) switching configuration comprising:

a first throw;

a second throw;

a pole;

a first switch arm segment implemented between the first throw and the pole, the first switch arm segment including a stack of field-effect transistor (FET) devices having a plurality active FETs, individual active FETs having a proximity electrode configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET;

a second switch arm segment implemented between the pole and the second throw, the second switch arm segment including a stack of field-effect transistor (FET) devices having a plurality active FETs, individual active FETs having a proximity electrode configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET;

a first shunt arm segment implemented between the first throw and a reference potential node, the first shunt arm segment including a stack of field-effect transistor (FET) devices having a plurality active FETs, individual active FETs having a proximity electrode configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET; and

a second shunt arm segment implemented between the second throw and a reference potential node, the second shunt arm segment including a stack of field-effect transistor (FET) devices having a plurality active FETs, individual active FETs having a proximity electrode configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET.