NAND memory cell string having a stacked select gate structure and process for for forming same

1. A method of forming a memory cell string, comprising:

forming over a channel in a substrate:

a string of a plurality of wordlines, each wordline separated from the channel in the substrate by a first stack of layers;

a first select gate comprising a plurality of elements coupled to a first end of the string of the plurality of wordlines; and

a second select gate coupled to a second end of the string of the plurality of wordlines,

wherein distances between a first element of the first select gate and the string of the plurality of wordlines is the same as a distance that is formed between each of the wordlines in the string of the plurality of wordlines.

2. The method of claim 1 wherein forming the first select gate comprises forming the first element of the first select gate separated from the channel in the substrate by a second stack of layers, the second stack of layers having the same stoichiometric composition and thickness as the first stack of layers.

3. The method of claim 2 wherein the first element of the first select gate is the same size as each of the plurality of wordlines.

4. The method of claim 2 wherein forming the first select gate further comprises forming a second element separated from the string of the plurality of wordlines by the first element and from the channel in the substrate by a single layer gate dielectric.

5. The method of claim 4 wherein the first element and the second element of the first select gate comprise different sizes.

6. The method of claim 4 wherein the first element and the second element of the first select gate comprise equal sizes.

7. The method of claim 1 wherein the first stack of comprises an oxide-nitride-oxide (ONO) stack.

8. The method of claim 7 wherein the memory string is a NAND memory string wherein each of the plurality of wordlines comprises an ONO memory transistor separated from the ONO memory transistors in an adjacent wordline by source-drain junctions.

9. A method of forming a memory cell string, comprising:

forming over a channel in a substrate a string of a plurality of core cells serially connected along the channel, each core cell including an internal wordline separated from the channel by a stack of layers including a charge trapping layer;

forming a source select gate adjacent to a first end of the string of the plurality of core cells and a drain select gate adjacent to a second end of the string of the plurality of core cells,

wherein at least one of the source select gate or the drain select gate is a stacked select gate comprising a first gate formed over the stack of layers and proximal to the string of the plurality of core cells, and a second gate separated from the string of the plurality of core cells by the first gate, and wherein a distance between the first gate of the stacked select gate and the internal wordline of a first core cell in the plurality of core cells is substantially the same as distances between each internal wordline in the plurality of core cells.

10. The method of claim 9 wherein the second gate of the stacked select gate is separated from the substrate by a single layer dielectric.

11. The method of claim 9 wherein a distance between the first gate and the second gate is different than the distances between the first gate and the internal wordline of the first core cell.

12. A method of forming a memory cell string, comprising:

forming a stack of layers including a charge trapping layer over a substrate;

forming over the stack of layers a plurality of core cells serially connected in a string over the stack of layers, each core cell including an internal wordline separated from the substrate by the stack of layers; and

forming a source select gate adjacent to a first end of the string of the plurality of core cells and a drain select gate adjacent to a second end of the string of the plurality of core cells,

wherein at least one of the source select gate or the drain select gate is a stacked select gate comprising a first component formed over the stack of layers and proximal to the string of the plurality of core cells, and a second component separated from the string of the plurality of core cells by the first component.

13. The method of claim 12 wherein a distance between the first component and the internal wordline of a first core cell in the string of the plurality of core cells is substantially the same as distances between each internal wordline in the string of the plurality of core cells.

14. The method of claim 12 wherein a distance between the first component and the second component is substantially the same as distances between the first component and the internal wordline of a first core cell and between each internal wordline in the string of the plurality of core cells.

15. The method of claim 12 wherein the first component and the second component comprise a same length along a direction co-axial with the string of the plurality of core cells.

16. The method of claim 12 wherein the first component and the second component comprise a different length along a direction co-axial with the string of the plurality of core cells.

17. The method of claim 12 wherein the first component and the second component comprise a different length along a direction co-axial with the string of the plurality of core cells.

18. The method of claim 12 wherein the second gate of the second component is separated from the substrate by a single layer dielectric.