Low-Temperature Dopant Activation Process Using a Cap Layer, and MOS Devices Including the Cap Layer
A method of making a MOS device, a MOS device containing an aluminum nitride layer, and a CMOS circuit are disclosed. The method includes depositing an aluminum nitride layer on a structure including a silicon layer, depositing a dopant ink on the structure, and diffusing the dopant through the aluminum nitride layer into the silicon layer. The structure also includes a gate oxide layer on the silicon layer and a gate on the gate oxide layer. The dopant ink includes a dopant and a solvent. The MOS device includes a silicon layer, a gate oxide layer on the silicon layer, a gate on the gate oxide layer, and an aluminum nitride layer on the gate. The silicon layer includes a dopant on opposite sides of the gate.
A method of making a MOS device, comprising:
a) depositing an aluminum nitride layer on a structure comprising a silicon layer, a gate oxide layer on the silicon layer, and a gate on the gate oxide layer;
b) depositing a dopant ink on the structure, the dopant ink comprising a dopant and a solvent; and
c) diffusing the dopant through the aluminum nitride layer into the silicon layer.
2 . The method of claim 1 , further comprising making said structure by a process that comprises forming the gate oxide layer on the silicon layer, and forming the gate on the gate oxide layer.
3 . The method of claim 2 , wherein making said structure further comprises forming a sidewall spacer on side surfaces of the gate.
4 . The method of claim 2 , wherein making said structure further comprises forming the silicon layer on a substrate.
5 . The method of claim 4 , wherein forming the silicon layer comprises depositing a silicon-containing ink on the substrate, and the silicon-containing ink comprises a silane and a solvent in which the silane is soluble.
6 . The method of claim 11 , wherein the substrate comprises a sheet or foil of a metal, or a sheet, disc, wafer or film of a ceramic, a glass, or a polymer.
7 . The method of claim 1 , wherein the dopant ink comprises a dopant source, the solvent, and an acrylic or methacrylic polymer.
8 . The method of claim 1 , further comprising activating the dopant after diffusing the dopant into the silicon layer.
9 . The method of claim 8 , wherein the dopant is activated at a temperature of 600-740° C.
10 . The method of claim 8 , wherein the dopant is activated at a temperature of at least 50° C. below a minimum activation temperature of an identical device having a silicon oxide layer in place of the aluminum nitride layer under otherwise identical activation conditions, the silicon oxide layer having a thickness identical to that of the aluminum nitride layer.
11 . The method of claim 1 , wherein the aluminum nitride layer has a thickness of from 20-200 Å.
12 . The method of claim 1 , further comprising depositing a silicon dioxide layer on the aluminum nitride layer, wherein the method comprises depositing the dopant ink onto the silicon dioxide layer, and the dopant ink comprises a compound and/or precursor of boron or gallium.
13 . The method of claim 12 , wherein the method comprises making a plurality of PMOS devices and a plurality of NMOS devices, depositing the dopant ink comprises printing a PMOS ink comprising (i) the compound and/or precursor of boron or gallium and (ii) a first solvent on the silicon oxide layer over structures corresponding to said PMOS devices, and the method further comprises:
removing the silicon oxide layer after diffusing the boron or gallium dopant through the aluminum nitride layer into the silicon layer corresponding to said PMOS devices;
printing an NMOS ink comprising (i) a compound and/or precursor of antimony, arsenic, or phosphorous and (ii) a second solvent onto the aluminum nitride layer over structures corresponding to said NMOS devices; and
diffusing the antimony, arsenic, or phosphorous dopant through the aluminum nitride layer into the silicon layer corresponding to said NMOS devices.
14 . The method of claim 1 , wherein the method further comprises removing the aluminum nitride layer after diffusing the dopant into the silicon layer.
15 . A MOS device, comprising:
a) a silicon layer,
b) a gate oxide layer on the silicon layer,
c) a gate on the gate oxide layer; and
d) an aluminum nitride layer on the gate,
wherein the silicon layer includes a dopant on opposite sides of the gate.
16 . The device of claim 15 , further comprising forming a sidewall spacer on side surfaces of the gate and an upper surface of the gate oxide layer.
17 . The device of claim 15 , wherein the silicon layer comprises a photolithographically-patterned or printed silicon island.
18 . The device of claim 15 , further comprising a substrate supporting the silicon layer, wherein the substrate comprises a sheet or foil of a metal, or a sheet, disc, wafer or film of a ceramic, a glass, or a polymer.
19 . The device of claim 15 , wherein the aluminum nitride layer has a thickness of from 20-200 Å.
20 . A CMOS circuit, comprising a plurality of the NMOS devices of claim 15 and a plurality of PMOS devices, wherein each of the PMOS devices comprises:
a) a separate silicon layer,
b) a separate gate oxide layer on the separate silicon layer,
c) a separate gate on the separate gate oxide layer; and
d) the aluminum nitride layer on the separate gate,
wherein the separate silicon layer includes a boron or gallium dopant on opposite sides of the separate gate.