Integrated ferroelectric capacitor/ field effect transistor structure

1. A method of forming a semiconductor structure, the method comprising:

providing a functional gate structure located on a surface of a semiconductor material portion and laterally surrounded by a middle-of-the-line (MOL) dielectric material;

recessing the functional gate structure to provide a capacitor cavity located above a remaining portion of the functional gate structure; and

forming a ferroelectric capacitor in the capacitor cavity, the ferroelectric capacitor comprising a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure, wherein the bottom electrode structure is located entirely beneath the U-shaped ferroelectric material liner.

2. The method of claim 1 , wherein a topmost surface of the MOL dielectric material is coplanar with a topmost surface of the functional gate structure.

3. The method of claim 1 , further comprising forming a contact structure above, and in contact with, at least the top electrode structure of the ferroelectric capacitor.

4. The method of claim 1 , wherein the forming the ferroelectric capacitor comprises:

forming a material stack of, from bottom to top, a bottom electrode material layer, and a ferroelectric material layer in the capacitor cavity and above a topmost surface of the MOL dielectric material;

forming an organic planarizing layer (OPL) on the ferroelectric material layer;

removing the OPL, the ferroelectric material layer, and the bottom electrode material layer from above the topmost surface of the MOL dielectric material, while maintaining portions of the OPL, the ferroelectric material layer, and the bottom electrode material layer in the capacitor cavity;

removing vertical extending portions of the remaining portion of the bottom electrode material layer in the capacitor cavity to provide a first opening located in a first portion of the capacitor cavity and a second opening located in a second portion of the capacitor cavity;

forming a dielectric spacer in each of the first and second openings;

removing the remaining portion of the OPL from the capacitor cavity; and

forming the top electrode structure in a volume previously occupied by the remaining portion of the OPL.

5. The method of claim 1 , wherein the forming the ferroelectric capacitor comprises:

forming a bottom electrode material layer in the capacitor cavity and above a topmost surface of the MOL dielectric material;

forming an organic planarizing layer (OPL) on the bottom electrode material layer;

removing the OPL and the bottom electrode material layer from above the topmost surface of the MOL dielectric material, while maintaining a portion of the OPL and a portion of the bottom electrode material layer in the capacitor cavity;

removing vertical extending portions of the remaining portion of the bottom electrode material layer in the capacitor cavity;

removing the remaining portion of the OPL from the capacitor cavity; and

forming the U-shaped ferroelectric material liner and the top electrode structure.

6. The method of claim 1 , wherein the remaining portion of the functional gate structure comprises a U-shaped gate dielectric portion, a U-shaped workfunction metal portion located on the U-shaped gate dielectric portion, and a gate electrode portion located on the U-shaped workfunction metal portion.

7. The method of claim 6 , wherein the U-shaped gate dielectric portion, the U-shaped workfunction metal portion and the gate electrode portion have topmost surfaces that are coplanar with each other.

8. The method of claim 1 , wherein the semiconductor material portion is a semiconductor fin.

9. The method of claim 1 , wherein the bottom electrode structure extends across an entirety of the topmost surface of the functional gate structure.

10. The method of claim 1 , wherein the bottom electrode structure partially extends across the topmost surface of the functional gate structure.

11. The method of claim 1 , wherein an insulator layer is located directly beneath the semiconductor material portion.

12. The method of claim 1 , wherein a punch-through stop layer is located directly beneath the semiconductor material portion.

13. The method of claim 12 , wherein the punch-through stop layer comprises a semiconductor material that is doped with a p-type.

14. The method of claim 12 , wherein the punch-through stop layer comprises a semiconductor material that is doped with an n-type dopant.

15. The method of claim 1 , wherein the recessing of the functional gate structure to provide the capacitor cavity comprises one or more etching processes.

16. The method of claim 1 , wherein the U-shaped ferroelectric material liner comprises a material that generates a negative capacitance.

17. The method of claim 16 , wherein the material that generates the negative capacitance comprises BaTiO 3 , Pb[Zr x Ti 1-x ]O 3 (0≤x≤1), or crystalline HfO 2 with a doping element selected from Zr, Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, and Y.

18. The method of claim 1 , wherein the bottom electrode structure and the top electrode structure comprises TiN, and wherein the functional gate structure includes a gate electrode portion composed of tungsten or titanium.