Switching regulator including an offset enabled comparison circuit
A switching regulator includes: an error amplification circuit configured to amplify a difference between a voltage based on the output voltage and a first reference voltage to output an error voltage; a PFM comparison circuit configured to compare the error voltage with a second reference voltage to output a comparison result signal at a first level or a second level, an offset being given to the error voltage for a given period in response to a change of the comparison result signal from the second level to the first level; an oscillation circuit configured to output a clock signal of a given frequency according to the first level of the comparison result signal, and to stop outputting the clock signal according to the second level of the comparison result signal; and a PWM conversion circuit configured to turn the switching element on at a prescribed pulse width.
1. A switching regulator that controls a switching element connected between a power supply terminal having a power supply voltage and one end of an inductor, and is configured to generate an output voltage at an output terminal that is connected to another end of the inductor, the switching regulator comprising:
an error amplification circuit configured to amplify a difference between a voltage based on the output voltage and a first reference voltage and to output an error voltage;
a pulse width modulation (PWM) conversion circuit including a control circuit;
a pulse frequency modulation (PFM) comparison circuit configured to compare the error voltage with a second reference voltage and to output a comparison result signal to the control circuit at one of a first level and a second level, where an offset voltage is combined with the error voltage by the control circuit and input to the PFM comparison circuit for a given period in response to a change of the comparison result signal from the second level to the first level, the offset voltage having a negative value relative to the second reference voltage; and
an oscillation circuit configured to output a clock signal of a given frequency according to the first level of the comparison result signal, and to stop outputting the clock signal according to the second level of the comparison result signal,
wherein the PWM conversion circuit is configured to turn the switching element on at a prescribed pulse width, based on the error voltage and on the output from the oscillation circuit.
2. The switching regulator according to claim 1 , wherein the offset voltage applied to an input to the PFM comparison circuit switches the comparison result signal to the second level.
3. The switching regulator according to claim 2 , wherein the PFM comparison circuit is configured to switch from a state in which the error voltage is compared with the second reference voltage to a state in which a voltage obtained by adding the offset voltage to the error voltage is compared with the second reference voltage, in response to the change of the comparison result signal from the second level to the first level.
4. The switching regulator according to claim 2 , wherein the PFM comparison circuit selects an absence and a presence of a hysteresis and is configured to enter a state in which the PFM comparison circuit has the hysteresis in response to the change of the comparison result signal from the second level to the first level.
5. The switching regulator according to claim 2 , wherein the PFM comparison circuit is configured to switch from a state in which the error voltage is compared with the second reference voltage to a state in which the error voltage is compared with a third reference voltage that differs from the second reference voltage in response to the change of the comparison result signal from the second level to the first level.
6. The switching regulator according to claim 1 , wherein the PFM comparison circuit is configured to switch from a state in which the error voltage is compared with the second reference voltage to a state in which a voltage obtained by adding the offset voltage to the error voltage is compared with the second reference voltage, in response to the change of the comparison result signal from the second level to the first level.
7. The switching regulator according to claim 1 , wherein the PFM comparison circuit selects an absence and a presence of a hysteresis and is configured to enter a state in which the PFM comparison circuit has the hysteresis in response to the change of the comparison result signal from the second level to the first level.
8. The switching regulator according to claim 1 , wherein the PFM comparison circuit is configured to switch from a state in which the error voltage is compared with the second reference voltage to a state in which the error voltage is compared with a third reference voltage that differs from the second reference voltage in response to the change of the comparison result signal from the second level to the first level.