Pixel and display device including the same
A pixel, wherein: gates of second and fifth transistors receive a first gate signal; gates of third and fourth transistors respectively receive second and third gate signals; first terminals (FTs) of the second to fifth transistors respectively receive a data voltage, reference voltage, initialization voltage, and first power supply voltage (PSV); a second electrode of a second capacitor receives the first PSV; a second terminal (ST) of a light emitting element (LEE) receives a second PSV; a gate of a first transistor, STs of the second and third transistors, and a first electrode of a first capacitor are connected to a first node; STs of the first and fourth transistors, a FT of the LEE, and second and first electrodes respectively of the first and second capacitors are connected to a second node; and a ST of the fifth transistor is connected to a FT of the first transistor.
1. A pixel comprising:
a first transistor comprising a gate connected to a first node, a first terminal, and a second terminal connected to a second node;
a second transistor comprising a gate configured to receive a first gate signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node;
a third transistor comprising a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node;
a fourth transistor comprising a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the second node;
a fifth transistor comprising a gate configured to receive the first gate signal, a first terminal configured to receive a first power supply voltage, and a second terminal connected to the first terminal of the first transistor;
a first capacitor comprising a first electrode connected to the first node, and a second electrode connected to the second node;
a second capacitor comprising a first electrode connected to the second node, and a second electrode configured to receive the first power supply voltage; and
a light emitting element comprising a first terminal connected to the second node, and a second terminal configured to receive a second power supply voltage.
2. The pixel of claim 1 , wherein:
the second transistor is configured to turn on in response to a first logic level of the first gate signal; and
the fifth transistor is configured to turn on in response to a second logic level of the first gate signal, the second logic level being different from the first logic level.
3. The pixel of claim 2 , wherein:
the second transistor is an n-channel metal oxide semiconductor (MOS) transistor; and
the fifth transistor is a p-channel MOS transistor.
4. The pixel of claim 3 , wherein the third transistor and the fourth transistor are n-channel MOS transistors.
5. The pixel of claim 4 , wherein the first power supply voltage is greater than the reference voltage, the initialization voltage, and the data voltage.
6. The pixel of claim 1 , wherein:
the second transistor is configured to receive the data voltage through a data line; and
the third transistor is configured to receive the reference voltage through a reference voltage line different from the data line.
7. The pixel of claim 1 , wherein the reference voltage is greater than the initialization voltage.
8. The pixel of claim 1 , wherein the first transistor further comprises a second gate connected to the second node.
9. The pixel of claim 1 , wherein the first transistor is an n-channel MOS transistor.
10. A display device comprising:
a display panel comprising a plurality of pixels; and
a panel driver configured to drive the display panel,
wherein at least one pixel among the pixels comprises:
a first transistor comprising a gate connected to a first node, a first terminal, and a second terminal connected to a second node;
a second transistor comprising a gate configured to receive a first gate signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node;
a third transistor comprising a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node;
a fourth transistor comprising a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the second node;
a fifth transistor comprising a gate configured to receive the first gate signal, a first terminal configured to receive a first power supply voltage, and a second terminal connected to the first terminal of the first transistor;
a first capacitor comprising a first electrode connected to the first node, and a second electrode connected to the second node;
a second capacitor comprising a first electrode connected to the second node, and a second electrode configured to receive the first power supply voltage; and
a light emitting element comprising a first terminal connected to the second node, and a second terminal configured to receive a second power supply voltage.
11. The display device of claim 10 , wherein a frame period of the display device comprises:
a first period in which the first node and the second node are initialized;
a second period in which a threshold voltage of the first transistor is sensed;
a third period in which the data voltage is applied to the first transistor; and
a fourth period in which the light emitting element emits light based on the data voltage.
12. The display device of claim 11 , wherein a length of the second period is longer than one horizontal period.
13. The display device of claim 11 , wherein a length of the third period is one horizontal period.
14. The display device of claim 11 , wherein, in the first period:
the third transistor, the fourth transistor, and the fifth transistor are configured to be turned on; and
the second transistor is configured to be turned off.
15. The display device of claim 11 , wherein, in the second period:
the third transistor and the fifth transistor are configured to be turned on; and
the second transistor and the fourth transistor are configured to be turned off.
16. The display device of claim 11 , wherein, in the third period:
the second transistor is configured to be turned on; and
the third transistor, the fourth transistor and the fifth transistor are configured to be turned off.
17. The display device of claim 11 , wherein, in the fourth period:
the fifth transistor is configured to be turned on; and
the second transistor, the third transistor, and the fourth transistor are configured to be turned off.
18. The display device of claim 11 , wherein:
the second transistor is an n-channel metal oxide semiconductor (MOS) transistor; and
the fifth transistor is a p-channel MOS transistor.
19. The display device of claim 11 , wherein:
the second transistor is configured to receive the data voltage through a data line; and
the third transistor is configured to receive the reference voltage through a reference voltage line different from the data line.
20. The display device of claim 11 , wherein the first transistor further comprises a second gate connected to the second node.
21. A pixel comprising:
a first transistor comprising a gate connected to a first node, a first terminal, and a second terminal connected to a second node;
a second transistor comprising a gate configured to receive a first gate signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node;
a third transistor comprising a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node;
a fourth transistor comprising a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the second node;
a fifth transistor comprising a gate configured to receive a fourth gate signal, a first terminal configured to receive a first power supply voltage, and a second terminal connected to the first terminal of the first transistor;
a first capacitor comprising a first electrode connected to the first node, and a second electrode connected to the second node;
a second capacitor comprising a first electrode connected to the second node, and a second electrode configured to receive the first power supply voltage; and
a light emitting element comprising a first terminal connected to the second node, and a second terminal configured to receive a second power supply voltage.