Techniques for laser alignment in photonic integrated circuits
Techniques for efficient alignment of a semiconductor laser in a Photonic Integrated Circuit (PIC) are disclosed. In some embodiments, a photonic integrated circuit (PIC) may include a semiconductor laser that includes a laser mating surface, and a substrate that includes a substrate mating surface. A shape of the laser mating surface and a shape of the substrate mating surface may be configured to align the semiconductor laser with the substrate in three dimensions.
1. A photonic integrated circuit (PIC), comprising:
a semiconductor laser comprising a laser mating surface and a contact surface, the laser mating surface comprising a tapered laser mating surface and a laser facet, the laser facet being completely set back to a position between where the tapered laser mating surface is narrower and the tapered laser mating surface is wider; and
a substrate comprising a tapered substrate mating surface and a recessed landing area formed in the substrate, wherein the tapered substrate mating surface is configured to contact the tapered laser mating surface of the semiconductor laser, and wherein the recessed landing area comprises a contact pad configured to form an electrical connection with the contact surface of the semiconductor laser.
2. The PIC of claim 1 , wherein a shape of the tapered laser mating surface and a shape of the tapered substrate mating surface are configured to align the semiconductor laser with the substrate when an external force is applied to the semiconductor laser.
3. The PIC of claim 2 , wherein an edge of the tapered laser mating surface is configured to contact the tapered substrate mating surface when the semiconductor laser is aligned with the substrate.
4. The PIC of claim 3 , wherein a rear wall of the substrate is configured to contact a back portion of the semiconductor laser and a side wall of the substrate is configured to contact a side surface of the semiconductor laser when the semiconductor laser is aligned with the substrate.
5. The PIC of claim 4 , wherein a portion of the side surface of the semiconductor laser is configured to be located above a gap portion of the substrate when the semiconductor laser is aligned with the substrate.
6. The PIC of claim 1 , wherein a first edge of the tapered laser mating surface contacts the tapered substrate mating surface, and a second edge of the tapered laser mating surface does not contact the tapered substrate mating surface.
7. The PIC of claim 1 , wherein the tapered substrate mating surface includes a curved edge, wherein the curved edge is configured to distribute an external force applied to the semiconductor laser during an alignment of the semiconductor laser with the substrate.
8. The PIC of claim 1 , further comprising:
a waveguide formed on the substrate, wherein the waveguide is configured to receive a laser beam that exits the laser facet.
9. The PIC of claim 8 , wherein the laser facet is angled and a leading edge of the waveguide is angled, and wherein the angle of the laser facet and the angle of the leading edge of the waveguide are configured to reduce a back reflection of the laser beam from the waveguide into the laser facet.
10. The PIC of claim 9 , wherein the laser facet and the leading edge of the waveguide are angled in the same direction.
11. The PIC of claim 1 , wherein solder is located between the contact pad and the contact surface of the semiconductor laser.
12. The PIC of claim 1 , wherein the recessed landing area further comprises:
a solder layer located on the contact pad; and
a run-off area configured to receive solder from the solder layer located on the contact pad.
13. The PIC of claim 12 , wherein the run-off area is configured to receive solder by drawing the solder from the solder layer away from the contact pad.
14. A method of fabricating a photonic integrated circuit (PIC), the method comprising:
arranging a semiconductor laser on a substrate, wherein the semiconductor laser comprises a laser mating surface and a contact surface, the laser mating surface comprising a tapered laser mating surface and a laser facet, the laser facet being completely set back to a position between where the tapered laser mating surface is narrower and the tapered laser mating surface is wider, wherein:
the substrate comprises a tapered substrate mating surface formed in the substrate and a recessed landing area;
the tapered laser mating surface is configured to contact the tapered substrate mating surface; and
the recessed landing area comprises a contact pad configured to form an electrical connection with the contact surface of the semiconductor laser; and
aligning the semiconductor laser with the substrate using a shape of the laser mating surface and a shape of the substrate mating surface.
15. The method of claim 14 , further comprising:
applying an external force to the semiconductor laser in a direction from the semiconductor laser toward the substrate.
16. The method of claim 15 , further comprising distributing the external force using a curved edge of the substrate mating surface.
17. The method of claim 14 , further comprising:
depositing solder on the contact surface of the semiconductor laser prior to arranging the semiconductor laser on the substrate, wherein:
arranging the semiconductor laser on the substrate includes electrically connecting the contact surface of the semiconductor laser to the contact pad of the substrate; and
the solder is located between the contact surface and the contact pad.
18. The method of claim 17 , wherein a surface tension of the solder draws the tapered laser mating surface into attachment with the tapered substrate mating surface.
19. A photonic integrated circuit (PIC) substrate, comprising:
a recessed landing area formed in the substrate; and
a waveguide formed in at least one material layer on the substrate and configured to receive an optical signal produced by a semiconductor laser, wherein:
the at least one material layer comprises a tapered substrate mating surface;
a shape of the tapered substrate mating surface corresponds to a shape of a tapered mating surface of the semiconductor laser to align the semiconductor laser with the substrate; and
a front edge of the waveguide is completely positioned between where the tapered substrate mating surface is narrower and the tapered substrate mating surface is wider.
20. The PIC substrate of claim 19 , wherein the waveguide includes an angled front edge.
21. The PIC substrate of claim 19 , wherein the shape of the tapered substrate mating surface is configured to contact a first edge of the semiconductor laser and preserve a space between the tapered substrate mating surface and a second edge of the semiconductor laser.
22. The PIC substrate of claim 19 , wherein the tapered substrate mating surface includes a curved edge configured to distribute an external force applied to the semiconductor laser during an alignment of the semiconductor laser with the substrate.
23. A semiconductor laser, comprising:
an active region sandwiched between an upper cladding layer and a lower cladding layer;
a laser mating surface comprising a tapered laser mating surface formed through etching and configured to align the semiconductor laser with a tapered substrate mating surface formed on a substrate, wherein a shape of the tapered laser mating surface corresponds to a shape of the tapered substrate mating surface; and
an etched laser facet configured to exit a laser beam produced by the semiconductor laser for receipt by a waveguide formed on the substrate, the etched laser facet being completely set back to a position between where the tapered laser mating surface is narrower and the tapered laser mating surface is wider.
24. The semiconductor laser of claim 23 , wherein a first edge of the tapered laser mating surface is configured to contact the tapered substrate mating surface when the semiconductor laser is aligned with the substrate.
25. The semiconductor laser of claim 24 , wherein a back portion of the semiconductor laser is configured to contact a rear wall of the substrate when the semiconductor laser is aligned with the substrate.
26. The semiconductor laser of claim 25 , wherein a side surface of the semiconductor laser is configured to contact a side wall of the substrate when the semiconductor laser is aligned with the substrate.
27. The semiconductor laser of claim 26 , wherein a portion of the side surface of the semiconductor laser is configured to be located above a gap portion of the substrate when the semiconductor laser is aligned with the substrate.
28. The semiconductor laser of claim 27 , wherein a second edge of the tapered laser mating surface is configured not to contact the tapered substrate mating surface.
29. The semiconductor laser of claim 23 , further comprising:
a contact surface configured to form an electrical connection with the substrate.
30. The semiconductor laser of claim 29 , further comprising:
a semiconductor contact layer above the upper cladding layer; and
a metallic contact layer, wherein a surface of the metallic contact layer is the contact surface.
31. The semiconductor laser of claim 30 , wherein the upper cladding layer is configured to keep optical loss due to the semiconductor contact layer and metallic contact layer less than 0.3/cm.
32. The semiconductor laser of claim 30 , wherein the metallic contact layer comprises two electrodes.
33. The semiconductor laser of claim 32 , wherein a first electrode of the two electrodes corresponds to a p-contact of the semiconductor laser and a second electrode of the two electrodes corresponds to an n-contact of the semiconductor laser.